Energy Efficient Architecture for Graph Analytics Accelerators

Abstract

Specialized hardware accelerators can significantly improve the performance and power efficiency of compute systems. In this paper, we focus on hardware accelerators for graph analytics applications and propose a configurable architecture template that is specifically optimized for iterative vertex-centric graph applications with irregular access patterns and asymmetric convergence. The proposed architecture addresses the limitations of the existing multi-core CPU and GPU architectures for these types of applications. The SystemC-based template we provide can be customized easily for different vertex-centric applications by inserting application-level data structures and functions. After that, a cycle-accurate simulator and RTL can be generated to model the target hardware accelerators. In our experiments, we study several graph-parallel applications, and show that the hardware accelerators generated by our template can outperform a 24 core high end server CPU system by up to 3x in terms of performance. We also estimate the area requirement and power consumption of these hardware accelerators through physical-aware logic synthesis, and show up to 65x better power consumption with significantly smaller area.

HyGCN: A GCN Accelerator with Hybrid Architecture

“…The area, power, and access latency of the on-chip scratchpad memory are estimated using Cacti 6.5 [1]. Since Cacti only supports down to 32 nm technologies, we apply four different scaling factors to convert them to 12 nm technology as shown in [33,36]. The energy of HBM 1.0 is estimated with 7 pJ/bit as in [32,41].…”

“…GCNs demand specialized architecture design. With the emergence of graph analytics and neural networks workloads, a lot of hardware architecture designs are proposed to accelerate these workloads [7,8,17,22,33]. For example, Graphicionado [17] is tailored for graph analtyics; while TPU [22] focuses on the acceleration of neural networks.…”

A Survey on Graph Processing Accelerators: Challenges and Opportunities

“…If incoming edges are used in the edge array, this layout is called Compressed Sparse Column (CSC). The compressed adjacency list graph is relatively compact and beneficial to many graph accelerators [29,71] . Note that the edges of each vertex are stored sequentially.…”

“…Specifically in terms of graph processing, it has been also witnessed that a large number of relevant studies build their graph processing accelerators based on FPGA [24][25][26][27][28] and ASIC [16,[29][30][31] . Evaluation on these http://www.riscv.org, Jan. 2019.…”

“…Nevertheless, existing studies on CPUs and GPUs have a wealth of experiences in designing graph accel-erators (as discussed in the previous studies [28][29][30]32] ).…”