Energy-efficient and two-step structure switching scheme based on reference-free for SAR ADC

Ding, Ruixue; Dong, Shaopeng; Sun, Depeng; Liu, Shubin; Zhu, Zhangming

doi:10.1007/s10470-019-01420-2

Cited by 6 publications

(6 citation statements)

References 10 publications

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“…As the sampling frequency increases the FoM decreases and power dissipation will be increased. Compared with reference [23][24][25] this ADC FoM achieves better results and the value is 3.15(fJ/conv-step) at 200kS/s sampling rate. This is due to the low power consumption of the proposed SAR-ADC.…”

Section: Resultsmentioning

confidence: 82%

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A 9.38-bit, 422nW, high linear SAR-ADC for wireless implantable system

Velagaleti¹,

Nayanathara²,

Madhavi

2021

TELKOMNIKA

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In wireless implantable systems (WIS) low power consumption and linearity are the most prominent performance metrics in data acquisition systems. successive approximation register-analog to digital converter (SAR-ADC) is used for data processing in WIS. In this research work, a 10-bit low power high linear SAR-ADC has been designed for WIS. The proposed SAR-ADC architecture is designed using the sample and hold (S/H) circuit consisting of a bootstrap circuit with a dummy switch. This SAR-ADC has a dynamic latch comparator, a split capacitance digital to analog converter (SC-DAC) with mismatch calibration, and a SAR using D-flipflop. This architecture is designed in 45 nm CMOS technology. This ADC reduces non-linearity errors and improve the output voltage swing due to the usage of a clock booster and dummy switch in the sample and hold. The calculated outcomes of the proposed SAR ADC display that with on-chip calibration an ENOB of 9.38 (bits), spurious free distortion ratio (SFDR) of 58.621 dB, and ± 0.2 LSB DNL and ± 0.4LSB INL after calibration.

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Section: Resultsmentioning

confidence: 82%

“…Table-I enumerates the functioning parameters of the SAR ADC with other reference papers. Another performance parameter is figure of Merit[22,23] and it can be characterized as;…”

mentioning

confidence: 99%

A 9.38-bit, 422nW, high linear SAR-ADC for wireless implantable system

Velagaleti¹,

Nayanathara²,

Madhavi

2021

TELKOMNIKA

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“…Successive approximation register (SAR) analog‐to‐digital converters (ADCs) generally consume low power in medium resolutions and bandwidths, 1–8 and this property makes them suitable for an extensive variety of applications specifically in energy‐limited applications, 1 multichannel neural recording systems, 2 wearable sensors, 3 and low energy wireless sensor network chips 4 . In charge‐redistribution SAR ADCs, the power consumption of the capacitor switching in the digital‐to‐analog converter (DAC) usually is dominant 1–5,9–15 . Recently, several techniques have been presented to reduce the DAC switching energy and capacitor size 1–26 …”

Section: Introductionmentioning

confidence: 99%

“…In charge‐redistribution SAR ADCs, the power consumption of the capacitor switching in the digital‐to‐analog converter (DAC) usually is dominant 1–5,9–15 . Recently, several techniques have been presented to reduce the DAC switching energy and capacitor size 1–26 …”

Section: Introductionmentioning

confidence: 99%

“…In Mao et al, 3 a multisegmentation DAC with a hybrid switching scheme is proposed to reduce the total number of the unit capacitors. A two‐step architecture with an MSB capacitor splitting and monotonic switching scheme is used in Ding et al 5 to reduce the total capacitance size and DAC area. The MSB‐splitting DAC and the LSB‐down techniques are combined in Wang and Wu 6 for switching energy reduction.…”

Section: Introductionmentioning

confidence: 99%

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Shifting the sampled input signal in successive approximation register analog‐to‐digital converters to reduce the digital‐to‐analog converter switching energy and area

Momeni

Yavari

2020

Circuit Theory & Apps

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Summary In this paper, a switching scheme is presented to reduce the capacitive digital‐to‐analog converter (DAC) switching energy, area, and the number of switches in successive approximation register (SAR) analog‐to‐digital converters (ADCs). In the proposed DAC switching method, after a few most significant bits (MSBs) decision, the sampled differential input signal is shifted into two special regions where the required DAC switching energy and area is less than the other regions. This technique can be utilized in most of the previously reported DAC switching schemes to further reduce the capacitive DAC switching energy and area. The conventional and two recently presented DAC switching techniques are utilized in the proposed SAR ADC to evaluate its usefulness.

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