2015
DOI: 10.1145/2723165
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Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage

Abstract: Spintronic memories are considered to be promising candidates for future on-chip memories due to their high density, nonvolatility, and near-zero leakage. However, they also face challenges such as high write energy and latency and limited read speed due to single-ended sensing. Further, the conflicting requirements of read and write operations lead to stringent design constraints that severely compromises their benefits.Recently, domain wall memory was proposed as a spintronic memory that has a potential for … Show more

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Cited by 5 publications
(2 citation statements)
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References 39 publications
(38 reference statements)
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“…Other research [37,39,40,45], closer to ours, pursue to completely remove the shift latency in DWM L1 caches. This is mainly accomplished by deploying as many access headers as bits stored in the DWM L1 cache.…”
Section: Introductionmentioning
confidence: 92%
See 1 more Smart Citation
“…Other research [37,39,40,45], closer to ours, pursue to completely remove the shift latency in DWM L1 caches. This is mainly accomplished by deploying as many access headers as bits stored in the DWM L1 cache.…”
Section: Introductionmentioning
confidence: 92%
“…Prior work focusing on L1 caches usually exploit the 1-bit DWM technology, where as many headers as number of bits are implemented to completely remove the shift latency at the cost of sacrificing storage capacity for a given die area [39,40].…”
Section: Related Workmentioning
confidence: 99%