Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches

Oboril, Fabian; Hameed, Fazal; Bishnoi, Rajendra; Ahari, Ali; Naeimi, Helia; Tahoori, Mehdi B.

doi:10.1145/2934583.2934629

Cited by 3 publications

(1 citation statement)

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“…In particular, standby power of the constituent caches account for much proportion in that of logic systems, and thus its reduction is considerably indispensable. Application of emerging nonvolatile memory such as spin-transfer torque magnetoresistive RAM (STT-MRAM) to caches can achieve extremely low standby power owing to its nonvolatile retention ability [2,3,4,5,6,7,8,9,10,11,12,13,14,15]. However, its high store energy and long store latency restrict the application to the last-level cache or main memory.…”

Section: Introductionmentioning

confidence: 99%

Proactive useless data flush architecture for nonvolatile SRAM using magnetic tunnel junctions

Kitagata

Yamamoto

Sugahara

2020

IEICE Electron. Express

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A store energy and latency reduction architecture based on proactive useless data flush (PUDF) is proposed for nonvolatile SRAM (NV-SRAM) using magnetic tunnel junctions (MTJs). Prior to the store operation to the MTJs in the array, the PUDF architecture predicts storeunneeded blocks having useless data and shuts down these blocks in advance. As a result, the store energy and latency can be reduced depending on the proportion of store-unneeded blocks, which enhances the energy reduction efficiency of power gating (PG) using the NV-SRAM. The energy and latency characteristics are computationally analysed and experimentally verified using circuit parameters extracted from fabricated test-element-group (TEG) circuits of the NV-SRAM.

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