Energy- and Area-Efficient CMOS Synapse and Neuron for Spiking Neural Networks With STDP Learning

Joo, Bomin; Han, Jin−Woo; Kong, Bai-Sun

doi:10.1109/tcsi.2022.3178989

Cited by 14 publications

(9 citation statements)

References 35 publications

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“…Under such circumstances, underflow can occur depending on the state of V mem . In previous studies, the membrane capacitor was typically connected to ground, preventing any possibility of underflow, as V mem could not go below 0 V. [25,26] However, in the proposed I&F neuron circuit, underflow is naturally allowed due to the fact that both electrodes of the membrane capacitor are not connected to 0 V but to V ref in the initial state. As a consequence, when a negative value of I in is applied, V mem becomes higher than V ref , which corresponds to the operation of UFA.…”

Section: Nm Cmos Iandf Neuron Circuitmentioning

confidence: 99%

“…While many studies have favored reduced membrane capacitance and V DD to achieve lower area and energy consumption per spike, our proposed I&F neuron circuit exhibits relatively higher area and energy consumption per spike in its current prototype stage. [26][27][28][29][30][31] However, through careful circuit optimization in simulation, we achieved a remarkable reduction of %47.2% in the neuron's area and an impressive 90% decrease in energy consumption per spike.…”

Section: Comparison To Previous Studiesmentioning

confidence: 99%

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Design of a 180 nm CMOS Neuron Circuit with Soft‐Reset and Underflow Allowing for Loss‐Less Hardware Spiking Neural Networks

Kim,

Kim

et al. 2023

Advanced Intelligent Systems

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Spiking neural networks (SNNs) have been researched as an alternative to reduce the gap with the human brain in terms of energy efficiency, due to their inherent spare event‐driven characteristics from a hardware implementation perspective. However, they still face significant challenges in learning, compared to artificial neural networks (ANNs). Recently, several algorithms have been developed to narrow the performance gap between SNNs and ANNs, including features in spiking neurons that can reduce information loss in the membrane potential. Inspired by these advancements, the current study designs and measures a neuron circuit using 180 nm complementary metal‐oxide‐semiconductor (CMOS) technology to address this information loss. The proposed circuit successfully implements these features, and their performance is validated through simulation based on the measured data.

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Section: Nm Cmos Iandf Neuron Circuitmentioning

confidence: 99%

Section: Comparison To Previous Studiesmentioning

confidence: 99%

Design of a 180 nm CMOS Neuron Circuit with Soft‐Reset and Underflow Allowing for Loss‐Less Hardware Spiking Neural Networks

Kim,

Kim

et al. 2023

Advanced Intelligent Systems

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“…In SNNs using analog eNeurons with high f spike , STDP learning curve can be illustrated in Fig. 2 [5], [6], [14]. There, a positive ∆T s less than 1 µs leads to a substantial increase in ∆w syn , while a negative ∆T s higher than -1 µs leads to a strong decrease in ∆w syn .…”

Section: B Stdp Learningmentioning

confidence: 99%

“…One of the biologically plausible learning rule is based on the occurrence time of spikes [5]. Among this category, the spike-timing-dependent plasticity (STDP) is a well-known rule that adjusts the strength of a synapse based on the relative time of pre-synaptic and post-synaptic spikes [6]. Previous studies have demonstrated that STDP is a powerful learning rule for SNNs, as it can be used for on-chip unsupervised learning [7].…”

Section: Introductionmentioning

confidence: 99%

Jitter Noise Impact on Analog Spiking Neural Networks: STDP Limitations

Jouni,

Rioufol,

Wang

et al. 2023

2023 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)

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Accurate spike timing of neurons is essential for the temporal learning rules in Spiking Neural Networks (SNNs), such as the spike-timing dependent plasticity (STDP). Implementing these rules in analog SNNs presents a challenge as it would require a reliable spike timing of analog neurons. This paper investigates the impact of jitter noise on the spike timing of various analog neuron models, and highlights trade-offs in training neurons using spike timing. Post-layout simulation results reveal that noise-induced period jitter significantly affects spike occurrence time. Its values are three orders of magnitude higher than the precise spike timing required for an accurate synaptic weight updates. Moreover, the spike timing becomes a random variable with a σ /µ that exceeds 76%. This study shows that the spiking frequency is a more reliable measure of neuronal activity, as it achieves a σ /µ of only 0.2%.

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“…For this reason, MI has been used consistently in neuroscience to show the modalities of information propagation in biological neural networks. On the other hand, much of the effort in neuromorphic electronics has been devoted to the design, development, and implementation of artificial CMOS [21] or memristive [22] neurons and either CMOS or memristive synapses [23][24][25] in circuits that embed specific learning rules and electrophysiological properties, paying less or no attention to the overall performance of the system under investigation from the standpoint of information transmission. In fact, understanding whether the currently proposed artificial SNNs can at least qualitatively replicate the extreme efficiency with which biological networks handle and transfer information represents an important step toward the development of brain-inspired and ultra-low-power artificial processing systems.…”

Section: Introductionmentioning

confidence: 99%

Biologically plausible information propagation in a complementary metal-oxide semiconductor integrate-and-fire artificial neuron circuit with memristive synapses

et al. 2023

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Neuromorphic circuits based on spikes are currently envisioned as a viable option to achieve brain-like computation capabilities in specific electronic implementations while limiting power dissipation given their ability to mimic energy efficient bio-inspired mechanisms. While several network architectures have been developed to embed in hardware the bio-inspired learning rules found in the biological brain, such as the Spike Timing Dependent Plasticity, it is still unclear if hardware spiking neural network architectures can handle and transfer information akin to biological networks. In this work, we investigate the analogies between an artificial neuron combining memristor synapses and rate-based learning rule with biological neuron response in terms of information propagation from a theoretical perspective. Bio-inspired experiments have been reproduced by linking the biological probability of release with the artificial synapses conductance. Mutual information and surprise have been chosen as metrics to evidence how, for different values of synaptic weights, an artificial neuron allows to develop a reliable and biological resembling neural network in terms of information propagation and analysis.

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Energy- and Area-Efficient CMOS Synapse and Neuron for Spiking Neural Networks With STDP Learning

Cited by 14 publications

References 35 publications

Design of a 180 nm CMOS Neuron Circuit with Soft‐Reset and Underflow Allowing for Loss‐Less Hardware Spiking Neural Networks

Design of a 180 nm CMOS Neuron Circuit with Soft‐Reset and Underflow Allowing for Loss‐Less Hardware Spiking Neural Networks

Jitter Noise Impact on Analog Spiking Neural Networks: STDP Limitations

Biologically plausible information propagation in a complementary metal-oxide semiconductor integrate-and-fire artificial neuron circuit with memristive synapses

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