Encoding neural and synaptic functionalities in electron spin: A pathway to efficient neuromorphic computing

Abstract

Present day computers expend orders of magnitude more computational resources to perform various cognitive and perception related tasks that humans routinely perform everyday. This has recently resulted in a seismic shift in the field of computation where research efforts are being directed to develop a neurocomputer that attempts to mimic the human brain by nanoelectronic components and thereby harness its efficiency in recognition problems. Bridging the gap between neuroscience and nanoelectronics, this paper attempts to provide a review of the recent developments in the field of spintronic device based neuromorphic computing. Description of various spin-transfer torque mechanisms that can be potentially utilized for realizing device structures mimicking neural and synaptic functionalities is provided. A cross-layer perspective extending from the device to the circuit and system level is presented to envision the design of an All-Spin neuromorphic processor enabled with on-chip learning functionalities. Device-circuit-algorithm co-simulation framework calibrated to experimental results suggest that such All-Spin neuromorphic systems can potentially achieve almost two orders of magnitude energy improvement in comparison to state-of-the-art CMOS implementations. Pinned Layers MTJ Pinned Layer Tunneling Oxide HM FL V SPIKE POST M STDP ∆G J ∆x J ∆x ∆G ∆x Device Characteristics ∆G ∆t ∆t J STDP Characteristics POST NEURON PRE V DD POST V SPIKE POST M STDP GND PRE V DD POST (t1) J Spike Transmission Mode Programming Mode T 2 T 3 T 1 MTJ Pinned Layer Tunneling Oxide HM FL ∆G J J p(∆G) Device Characteristics ∆G ∆t ∆t J STDP Characteristics 0 10 20

Comparing domain wall synapse with other non volatile memory devices for on-chip learning in analog hardware neural network

“…Next we design crossbar array based Fully Connected Neural Network (FCNN) with domain wall synapses [17] and compare the energy and speed performance for on-chip learning with that for equivalent FCNN designed with RRAM and PCM synapses. It is to be noted that this NN is of the second generation non-spiking type [49] and uses standard Stochastic Gradient Descent (SGD) algorithm for weight update [21]. Verilog-A model of domain wall synapse is designed, based on its conductance response obtained from micromagnetic physics as shown in Fig.…”

Photonic In-Memory Computing Primitive for Spiking Neural Networks Using Phase-Change Materials

“…However, the overhead of frequent data transport between the memory and processor have led to a shift in the computing paradigm as 'in-memory' computing platforms [8,9] attempt to emulate the 'massively parallel' operations of the brain. Although the term 'neuromorphic' was primarily coined [10] with CMOS technology in mind, this computing domain has branched out to nonvolatile memory (NVM) technologies such as oxide-based memristors [11], spintronics [12], phase change materials (PCM) [13,14], etc in the recent years. The natural ability of these resistive technologies to compute parallelized dot-products using crossbar structures make them promising candidates for neuromorphic systems.…”

All-Spin Bayesian Neural Networks

“…The average accuracy degradation was observed to be insignificant 1 The related code can be found at https://github.com/nitarshan/ bayes-by-backprop. 2 The Kullback-Leibler (KL) divergence is a measure of the difference between two probability distributions. In this case, the KL divergence is between the true posterior, P (W|D) and the approximated posterior q(W, θ).…”