Enabling Technology for On-Chip Interconnection Networks

The ReNoC Reconfigurable Network-on-Chip

“…-If the links use low-swing signaling, it is also possible to implement the topology switches using low-swing switches as presented in Dally [2007]. -If reconfiguration is expected to occur infrequently or only at initialization of the SoC platform, implementation styles similar to those used in FPGA switch boxes can be used for the TSs, such as pass-gates, tristate buffers, or multiplexers as shown in Figure 1(c).…”

Low Diameter Unicast On-Chip Interconnection Networks for Many-Core Embedded Systems

“…The router's power consumption is linear to the total bandwidth of its inputs [8]. Router power is dominant over wire propagation and buffer powers, motivating topologies with fewer hops and longer wires [4].…”

“…Reconfigurable networks are effective but like non-blocking crossbars are too costly. Dally [4] pointed to the need to design low diameter OCINs with small area and power costs. A low network diameter is certainly a prime requirement of real-time applications in embedded systems.…”

Session-Based Compilation Framework for Multicore Programming

“…One of the prominent recent examples include Cell microprocessor [35]. This model considers CMP as a microscopic form of distributed computing, and is capable of making the most of on-chip interconnect, suggesting its potential scalability when the number of cores per chip increases and a relative wire delay inside a chip takes effect [9]. It can realise arbitrary forms of data sharing among cores' local memories, and in that sense it is generalpurpose.…”

“…In a high-level view, this approach regards CMP as distributed parallel machines with explicit remote data transfer among them, making the framework close to computing models such as the LogP model [7] and parallel hierarchical memories [1]. The direct, asynchronous memory-to-memory transfer as a means of data exchange is flexible and can potentially make the most of on-chip network bandwidth [26], which is many-fold larger than intra-host computer networks [9], promoting concurrent, asynchronous use of communication and computing elements inside a chip. As has been studied in the literature [15-17, 30, 31], message passing concurrency can flexibly and generally represent the diverse forms of control and data flows found in sequential and concurrent applications.…”