Enabling Secure MPSoC Dynamic Operation through Protected Communication

Azad, Siavoosh Payandeh; Niazmand, Behrad; Jervan, Gert; Sepúlveda, Johanna

doi:10.1109/icecs.2018.8617940

Cited by 6 publications

(4 citation statements)

References 18 publications

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“…The object code integrity is usually achieved with message authentication codes (MAC). While spreading the application on MPSoC, each IP will verify the MAC individually [32]. SipHash-2-4 is one of the recommendations to avoid code injection attack [32].…”

Section: Secure Admission Of Applicationmentioning

confidence: 99%

See 1 more Smart Citation

Exploring the security landscape: NoC-based MPSoC to Cloud-of-Chips

Sharma

Bousdras

Ellinidou

et al. 2021

Microprocessors and Microsystems

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This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

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Section: Secure Admission Of Applicationmentioning

confidence: 99%

“…While spreading the application on MPSoC, each IP will verify the MAC individually [32]. SipHash-2-4 is one of the recommendations to avoid code injection attack [32]. The pre-stored MAC is compared with computed MAC-over the application memory block.…”

Section: Secure Admission Of Applicationmentioning

confidence: 99%

Exploring the security landscape: NoC-based MPSoC to Cloud-of-Chips

Sharma

Bousdras

Ellinidou

et al. 2021

Microprocessors and Microsystems

View full text Add to dashboard Cite

show abstract

“…Azad et al [40] propose a firewall to guarantee the platform's integrity and confidentiality. The firewall is placed at the NI and has two tables: (i) initiator table, which checks if the source has permission to send messages, and (ii) target table, which verifies if the message is allowed to enter the target unit.…”

Section: (I) Firewallsmentioning

confidence: 99%

A Survey on Security Mechanisms for NoC-based Many-Core SoCs

Caimi

Faccenda

Moraes

2021

JICS

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The adoption of many-cores systems introduces the concern for data protection as a critical design requirement due to the resource sharing and the simultaneous executions of several applications on the platform. A secure application that processes sensitive data may have its security harmed by a malicious process. The literature contains several proposals to protect many-cores against attacks, focusing on the protection of the application execution or the access to shared memories. However, there is a gap to be fulfilled: a solution covering the entire application lifetime, including its admission, execution, and peripheral's access. This survey discusses three security-related issues: the secure admission of applications, the prevention of resource sharing during their execution, and the safe access to external devices. This survey concludes with an evaluation of the studied methods, pointing out directions and research opportunities.

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“…Multiprocessor-System-on-Chip (MPSoC) and related on-chip networking architectures for communicating System-on-Chip (SoC) elements have been extensively investigated in the past [1]; however, their security is seldom mentioned [2]. The accuracy and security of the hardware, especially the processors, need to be enhanced because they suffer from attacks, and hardware mending is difficult or even unfeasible [3].…”

Section: Introductionmentioning

confidence: 99%

Encryption AXI Transaction Core for Enhanced FPGA Security

et al. 2022

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The current hot topic in cyber-security is not constrained to software layers. As attacks on electronic circuits have become more usual and dangerous, hardening digital System-on-Chips has become crucial. This article presents a novel electronic core to encrypt and decrypt data between two digital modules through an Advanced eXtensible Interface (AXI) connection. The core is compatible with AXI and is based on a Trivium stream cipher. Its implementation has been tested on a Zynq platform. The core prevents unauthorized data extraction by encrypting data on the fly. In addition, it takes up a small area—242 LUTs—and, as the core’s AXI to AXI path is fully combinational, it does not interfere with the system’s overall performance, with a maximum AXI clock frequency of 175 MHz.

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Enabling Secure MPSoC Dynamic Operation through Protected Communication

Cited by 6 publications

References 18 publications

Exploring the security landscape: NoC-based MPSoC to Cloud-of-Chips

Exploring the security landscape: NoC-based MPSoC to Cloud-of-Chips

A Survey on Security Mechanisms for NoC-based Many-Core SoCs

Encryption AXI Transaction Core for Enhanced FPGA Security

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