Exploring the security landscape: NoC-based MPSoC to Cloud-of-Chips

Sharma, Gaurav; Bousdras, Georgios; Ellinidou, Soultana; Markowitch, Olivier; Dricot, Jean‐Michel; Milojevic, Dragomir

doi:10.1016/j.micpro.2021.103963

Cited by 12 publications

(4 citation statements)

References 55 publications

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“…Because of the growing attention shown by academia and industry, research on DoS Attack Countermeasure techniques (DoS A-CTs) in the context of MPSoCs-based IoT remains scarce in the literature. The majority of published research articles have concentrated on the MPSoC communication security aspects and several expected Hardware Trojans (HTs) and other malicious circuits that may include in the MPSoC platforms by a disloyal member during the design or fabrication process [5]. Some studies have focused on the MPSoCs communication system routing protocols and routers aspects, highlighting the necessity of the proposed defenses techniques compatible with MPSoC design constraints or investigating the appropriate countermeasure technique for MPSoC in real runtime [6]- [9].…”

Section: B Challengesmentioning

confidence: 99%

Evaluation Approach for Efficient Countermeasure Techniques Against Denial-of-Service Attack on MPSoC-Based IoT Using Multi-Criteria Decision-Making

et al. 2023

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Context: Denial-of-Service Attack countermeasure techniques (DoS A-CTs) evaluation is a multi-criteria decision-making (MCDM) problem based on different MPSoCs of IoT platform design, performance, and design overhead. Therefore, the Fermatean by fuzzy decision opinion score method (F-FDOSM) for prioritizing the powerful countermeasure technique against Denial-of-Service (DoS) attack is the best approach because it employs the most efficient MCDM ranking technique. Nonetheless, the FDOSM method needs to weigh the criteria before being submitted for the ranking process. In order to address this theoretical challenge, the Criteria-importance through inter-criteria correlation (CRITIC) technique can be applied as an effective MCDM weighting technique to offer an explicit weight for a set of criteria with no inconsistency based on the standard deviation, which uses correlation analysis to determine the relevance of each criterion. Objectives: This research proposes a Fermatean-FDOSM framework for evaluating DoS A-CTs in the context of MPSoCs-based IoT and CRITIC techniques to weight the criteria. Methods: The methodology is presented in three phases. Firstly, a proposed countermeasure techniques dataset was collected that included eighteen defense approaches (e.g., Sniffer, SeRA, and RLAN) based on thirteen criteria (e.g., size, power, latency, and effectiveness ... etc.). Then, the decision matrix was built based on an intersection of the countermeasure techniques as an alternative and MPSoC design and performance criteria. Then, the multi-criteria decision-making methods were integrated. The CRITIC method for criteria weighting was followed by the development of the Fermatean-FDOSM method for ranking. Results: (1) CRITIC weighting shows that MPSoC NoC Routing Algorithm (XY and YX) is the highest weight criterion, whereas latency (clock/cycle) is the less weight criterion. ( 2) The Fermatean-FDOSM-based group ranking shows that the Collision Point Router Detection (CPRD) countermeasure technique is the first-ranked alternative compared to the Secure Model Checkers (SMCs) approach. (3) The DoS A-CTs priority ranks were subjected to a systematic ranking that was confirmed by solid correlation results throughout thirteen criterion weight values. A comparison with recent studies confirmed the feasibility of the proposed framework. Conclusion: The results of this research are expected to provide a specific understanding and guide for those who want to engage in MPSoCs-based IoT and NoC communication security research with decision theory.

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Section: B Challengesmentioning

confidence: 99%

Evaluation Approach for Efficient Countermeasure Techniques Against Denial-of-Service Attack on MPSoC-Based IoT Using Multi-Criteria Decision-Making

et al. 2023

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“…Sharma et al [15] analyze the security aspects of MP-SoCs, discussing several defense mechanisms known in the literature, such as secure zones, firewalls, and key agreement, and then expand the discussion to the Cloud of Chips scope. Furthermore, the authors propose a software-defined network-on-chip (SDNoC) as an alternative that can reserve resources, avoiding congestion and harmful paths.…”

Section: Related Workmentioning

confidence: 99%

A Comprehensive Framework for Systemic Security Management in NoC-Based Many-Cores

Faccenda,

Comarú,

Caimi

et al. 2023

IEEE Access

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Many-core Systems-on-Chip (MCSoC) are increasingly used in various applications domains such as high-performance computing, embedded systems, and Internet of Things devices. As MCSoCs permeate various industries and applications, the potential consequences of security issues are becoming increasingly severe. Therefore, security is a fundamental design constraint, addressing vulnerabilities and protecting valuable data from threats. This requires the development of robust security mechanisms and countermeasures against potential threats. The reviewed works on security for MCSoCs addressed frameworks and mechanisms to treat different security threats. Despite these proposals, the integration of security mechanisms still needs to be improved, enabling a security manager to make decisions using monitoring data for mitigating threats more effectively. This integration is the primary goal of our work, aiming to create a comprehensive framework for security management. The framework adopts a Monitoring-Detection-Countermeasure loop. A distributed monitoring infrastructure detects suspicious behaviors, generating warnings to different system actors. These actors decide the warning severity, firing security countermeasures. Countermeasures may be local (e.g., discarding a packet) or taken at the system level (e.g., aborting a malicious application). The results use an MCSoC modeled at the RTL level, providing accuracy at the clock cycle (cc) level. Five different attack scenarios are evaluated, showing that the gap between attack detection and countermeasure takes less than one millisecond (15,000 cc at 100 MHz). The area overhead in the communication infrastructure corresponds to 48.8%. These results show that the framework can effectively manage the system's security while maintaining the performance of the applications.INDEX TERMS Countermeasures, Monitoring, NoC-based Many-cores, Security Framework.

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“…As previously mentioned, these techniques enhance cache memory architecture's overall performance. When side-channel data are detected, the theoretical usage of cache memory on a side-channel based on cryptography is a possible option [20]. Simple text encryption allows for data hacking.…”

Section: A Security Issues In Cache Memorymentioning

confidence: 99%

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

et al. 2022

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This paper provides an overview of blockchain technology's security and privacy features, as well as an overview of IoT-based cache memory and single-bit six transistor static random-access memory cell sense amplifier architecture. Each chip's memory is used for recorded as blocks, which are encrypted and used as a blockchain for other memory devices. The architectures comprise of the circuit of write driver, six transistor static random access memory cells, and sense amplifiers such as current differential sense amplifier, charge transfer differential sense amplifier, and voltage latch sense amplifier. Furthermore, different parameters such as the number of transistors, sensing delay, and power consumption have been analyzed for varying resistance values (i.e., R=42.3 and R=42.3K ). Apart from that, power reduction techniques such as dual sleep, forced stack, sleep transistor, and sleep stack are used to optimize power consumption. These power reduction techniques are applied over different blocks of architecture, such as six transistors static random access memory cell and sense amplifier to optimize power consumption of the architecture. The conclusion arises that a single-bit six transistor static random access memory cell with power reduction dual sleep technique voltage latch sense amplifier with power reduction dual sleep technique in architecture consumes 11.65µW of power and has 33 transistors which are lowest from other architectures.INDEX TERMS Circuit of write driver (CWD), sense amplifier (SA), current differential sense amplifier (CDSA), charge transfer differential sense amplifier (CTDSA), voltage latch sense amplifier (VLSA), six transistor static random-access memory (6T-SRAM).

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Exploring the security landscape: NoC-based MPSoC to Cloud-of-Chips

Cited by 12 publications

References 55 publications

Evaluation Approach for Efficient Countermeasure Techniques Against Denial-of-Service Attack on MPSoC-Based IoT Using Multi-Criteria Decision-Making

Evaluation Approach for Efficient Countermeasure Techniques Against Denial-of-Service Attack on MPSoC-Based IoT Using Multi-Criteria Decision-Making

A Comprehensive Framework for Systemic Security Management in NoC-Based Many-Cores

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

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