Enabling parametric feasibility analysis in real-time calculus driven performance evaluation

Simalatsar, Alena; Ramadian, Yusi; Lampka, Kai; Perathoner, Simon; Thiele, Lothar

doi:10.1145/2038698.2038723

Cited by 9 publications

(9 citation statements)

References 38 publications

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“…There exist several system-level design methodologies helping to structure, plan, and control the process of developing an information system [8]- [10]. In this section we will focus on a frameworks allowing formal analysis of system properties essential for the design of safety-critical systems.…”

Section: A Design Methodologiesmentioning

confidence: 99%

Safe Implementation of Embedded Software for a Portable Device Supporting Drug Administration

Simalatsar

Bornet

You

et al. 2014

2014 IEEE International Conference on Bioinformatics and Bioengineering

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Abstract-Poor adherence to medical regimen causes approximately 33% to 69% of medication-related hospitalizations and accounts for $100 billion in annual health care costs. In this paper we address the problem of unintentional non adherence, when patient fails to take a medication due to forgetfulness or carelessness. We present the safe approach to software implementation of a portable reminder device with enabled personalization of medical regimen. The presented prototype is designed for imatinib administration, a drug used to treat Chronic Myeloid Leukemia (CML). However, thanks to the component-based structure of the software, the method can be applied to other cases by replacing implementation of certain components.

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Section: A Design Methodologiesmentioning

confidence: 99%

Safe Implementation of Embedded Software for a Portable Device Supporting Drug Administration

Simalatsar

Bornet

You

et al. 2014

2014 IEEE International Conference on Bioinformatics and Bioengineering

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“…It would be very interesting to explore the possibility of a parametric analysis in order to speed up the design-space exploration, along the lines that have been explored in [37,38].…”

Section: Methodsmentioning

confidence: 99%

Modeling Task Systems Using Parameterized Partial Orders

Houben

Igna

Vaandrager

2012

2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium

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Abstract. Inspired by work on model-based design of printers, the notion of a parametrized partial order (PPO) was introduced recently. PPOs are a simple extension of partial orders, expressive enough to compactly represent large task graphs with finite repetitive behavior. We present a translation of the PPO subclass to timed automata and prove that the transition system induced by the Uppaal models is isomorphic to the configuration structure of the original PPO. Moreover, we introduce real-time task systems (RTTS), a general model for real-time embedded systems that we have used to describe the data paths of realistic printer designs. In an RTTS, tasks are represented as PPOs and the pace of a task instance may vary, depending on the resources that are allocated to it. We describe a translation of a subclass of RTTSs to Uppaal, and establish, for an even smaller subclass, bisimulation equivalence between the timed configuration semantics of an RTTS and the transition system induced by the corresponding Uppaal translation. Lastly, we report on a series of experiments which demonstrates that the resulting Uppaal models are more tractable than handcrafted models of the same systems used in earlier case studies.

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“…Such techniques have been introduced in [19,20] for the combination of Timed Automata and RTC. The authors of [3] handle the case of synchronous data-flow component models and RTC and [36] introduces the coupling of parametric Timed Automata and RTC on top of a SMT-based analysis technique for deriving regions of parameters for task activation patterns under which the system is scheduled. Our analysis for real-time tasks in a multicore setting is based on the aforementioned coupling of Timed Automata (TA) [4] and RTC [19,20], where we exploit specific concepts as implemented in the timed model checker Uppaal [7,8].…”

Section: Related Workmentioning

confidence: 99%

A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets

et al. 2014

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A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets. Real-time systemshttp://dx.doi.org/10.1007/s11241-014-9211-y Access to the published version may require subscription. N.B. When citing this work, cite the original published paper. Abstract Multicore technology has the potential for drastically increasing productivity of embedded real-time computing. However, joint use of hardware, e.g., caches, memory banks and on-chip buses makes the integration of multiple real-time applications into a single system difficult: resource accesses are exclusive and need to be sequenced. Moreover, resource access schemes of modern off-the-shelf multicore chips are commonly optimized for the average-case, rather than being timing predictable. Real-time analysis for such architectures is complex, as execution times depend on the deployed hardware, as well as on the software executing on other cores. This will ask for significant abstractions in the timing analysis, where the resulting pessimism will lead to over-provisioned system designs and a lowered productivity as the number of applications to be put together into a single architecture needs to be decreased. In response to this, (a) we present a formal approach for bounding the worst-case response time of concurrently executing real-time tasks under resource contention and almost arbitrarily complex resource arbitration policies, with a focus on main memory as shared resource, (b) we present a simulation framework which allows for detailed modeling and empirical evaluation of modern multicore platforms and applications running on top of them, and (c) we present experiments to demonstrate the advantages and disadvantages of the presented methodologies and compare their accuracy. For limiting non-determinism inherent to the occurrence of cache misses, we particularly take advantage from the PRedictable Execution Model (PREM) as discussed in recent works.

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Enabling parametric feasibility analysis in real-time calculus driven performance evaluation

Cited by 9 publications

References 38 publications

Safe Implementation of Embedded Software for a Portable Device Supporting Drug Administration

Safe Implementation of Embedded Software for a Portable Device Supporting Drug Administration

Modeling Task Systems Using Parameterized Partial Orders

A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets

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