This paper presents a compositional and hybrid approach for the performance analysis of distributed real-time systems. The developed methodology abstracts system components by either flow-oriented and purely analytic descriptions or by state-based models in the form of timed automata. The interaction among the heterogeneous components is modeled by streams of discrete events. In total this yields a hybrid framework for the compositional analysis of embedded systems. It supplements contemporary techniques for the following reasons: (a) state space explosion as intrinsic to formal verification is limited to the level of isolated components; (b) computed performance metrics such as buffer sizes, delays and utilization rates are not overly pessimistic, because coarse-grained analytic models are used only for components that conform to the stateless model of computation. For demonstrating the usefulness of the presented ideas, a corresponding tool-chain has been implemented. It is used to investigate the performance of a two-staged computing system, where one stage exhibits state-dependent behavior that is only coarsely coverable by a purely analytic and stateless component abstraction. Finally, experiments are performed to ascertain the scalability and the accuracy of the proposed approach.
Energy consumption has become an important issue for modern embedded systems. This is because, one does not only like to deploy high-performance systems and provide guaranteed services, but also request system deployments to last as long as possible. With online dynamic power management (DPM), one adaptively changes the system's power mode, i. e., schedules when to turn on and off on-the-fly, to achieve energy savings. This paper introduces dynamic counters and discusses their usage in the context of (online) DPM in a setting where systems have to fulfill hard real-time requirements. The proposed scheme enables one to conservatively bound the future workload and thereby to safely schedule on-and off-periods of devices. Simulation results indicate that the proposed technique is more efficient and more effective with respect to energy savings, compared to previous work.
We propose a performance verification technique for cyberphysical systems that consist of multiple control loops implemented on a distributed architecture. The architectures we consider are fairly generic and arise in domains such as automotive and industrial automation; they are multiple processors or electronic control units (ECUs) communicating over buses like FlexRay and CAN. Current practice involves analyzing the architecture to estimate worst-case end-to-end message delays and using these delays to design the control applications. This involves a significant amount of pessimism since the worst-case delays often occur very rarely. We show how to combine functional analysis techniques with model checking in order to derive a delay-frequency interface that quantifies the interleavings between messages with worst-case delays and those with smaller delays. In other words, we bound the frequency with which control messages might suffer the worst-case delay. We show that such a delay-frequency interface enables us to verify much tigher control performance properties compared to what would be possible with only worst-case delay bounds.
Abstract. This article presents the results of the Model Checking Contest held within the SUMo 2011 workshop, a satellite event of Petri Nets 2011. This contest aimed at a fair and experimental evaluation of the performances of model checking techniques applied to Petri nets. The participating tools were compared on several examinations (state space generation, deadlock detection and evaluation of reachability formulae) run on a set of common models (Place/Transition and Symmetric Petri nets). The collected data gave some hints about the way techniques can scale up depending on both examinations and the characteristics of the models. This paper also presents the lessons learned from the organizer's point of view. It discusses the enhancements required for future editions of the Model Checking Contest event at the Petri Nets conference.
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