Enabling High-Performance Crossbars through a Floorplan-Aware Design

Roca, Antoni; Hern'ndez, Carles; Flich, José; Silla, Federico; Duato, J.

doi:10.1109/icpp.2012.24

Cited by 8 publications

(13 citation statements)

References 20 publications

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“…The latency values used for the tree and the bus reflect the improved scalability of the tree where arbitration is performed on a distributed manner and the maximum link length is decreased [23]. For modeling this processor setup we used a simulator based on the SoCLib simulation framework [26].…”

Section: Discussionmentioning

confidence: 99%

“…Among existing NoC designs, only buses have been proven MBPTA-compliant [12] for different arbitration policies. However, bus scalability is limited since its latency increases rapidly with the number of cores [23]. Further, in the context of MBPTA, proposed arbitration policies offer homogeneous guarantees and performance across cores, which do not match the heterogeneous bandwidth requirements in future mixed-criticality multicore real-time systems [28].…”

Section: Introductionmentioning

confidence: 99%

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pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems

Slijepcevic

Fernadez²,

Hernández

et al. 2016

2016 Euromicro Conference on Digital System Design (DSD)

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Abstract-The use of networks-on-chip (NoC) in real-time safety-critical multicore systems challenges deriving tight worstcase execution time (WCET) estimates. This is due to the complexities in tightly upper-bounding the contention in the access to the NoC among running tasks. Probabilistic Timing Analysis (PTA) is a powerful approach to derive WCET estimates on relatively complex processors. However, so far it has only been tested on small multicores comprising an onchip bus as communication means, which intrinsically does not scale to high core counts. In this paper we propose pTNoC, a new tree-based NoC design compatible with PTA requirements and delivering scalability towards medium/large core counts. pTNoC provides tight WCET estimates by means of asymmetric bandwidth guarantees for mixed-criticality systems with negligible impact on average performance. Finally, our implementation results show the reduced area and power costs of the pTNoC.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems

Slijepcevic

Fernadez²,

Hernández

et al. 2016

2016 Euromicro Conference on Digital System Design (DSD)

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“…MoT presents a low implementation cost as it just provides a single path between source and destination. This renders in faster implementations of the interconnect [6,19,20]. Additionally, these networks provide high throughput and low latency.…”

Section: Generic Mesh-of-treementioning

confidence: 99%

“…This MoT architecture achieves N flits/node/cycle throughput. In this sense, it resembles a registered crossbar which achieves maximum throughput [21,20] at the expense of increasing resources. The main difference is that a registered crossbar is typically managed by a central control unit which decides which input is connected to each output at a time.…”

Section: Network Implementationmentioning

confidence: 99%

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Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Roca

Hernández

Lodde

et al. 2015

Computers & Electrical Engineering

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Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the networkon-chip and the coherence protocol, improves performance and power meanwhile total area resources remain bounded. We propose a snoopy-aware network-onchip topology made of two mesh-of-tree topologies. Reducing the complexity of the coherence protocol -and hence its resources -, and moving this complexity to the network, leads to a global decrease in power consumption meanwhile area is barely affected. Benefits of our proposal are due to the high-throughput and low delay of the network, but also due to the simplicity of the coherence protocol. The proposed network and protocol minimizes communication amongst cores when compared to traditional solutions based either on 2D-mesh topologies or in directory-based protocols.

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Parallel many-core avionics systems

Panic

Quiñones

Zaykov

et al. 2014

Proceedings of the 14th International Conference on Embedded Software

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Integrated Modular Avionics (IMA) enables incremental qualification by encapsulating avionics applications into software partitions (SWPs), as defined by the ARINC 653 standard. SWPs, when running on top of single-core processors, provide robust time partitioning as a means to isolate SWPs timing behavior from each other. However, when moving towards parallel execution in many-core processors, the simultaneous accesses to shared hardware and software resources influence the timing behavior of SWPs, defying the purpose of time partitioning to provide isolation among applications. In this paper, we extend the concept of SWP by introducing parallel software partitions (pSWP) specification that describes the behavior of SWPs required when running in a many-core to enable incremental qualification. pSWP are supported by a new hardware feature called guaranteed resource partition (GRP) that defines an execution environment in which SWPs run and that controls interferences in the accesses to shared hardware resources among SWPs such that time composability can be guaranteed.

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Enabling High-Performance Crossbars through a Floorplan-Aware Design

Cited by 8 publications

References 20 publications

pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems

pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Parallel many-core avionics systems

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