Parallel many-core avionics systems

Abstract

Integrated Modular Avionics (IMA) enables incremental qualification by encapsulating avionics applications into software partitions (SWPs), as defined by the ARINC 653 standard. SWPs, when running on top of single-core processors, provide robust time partitioning as a means to isolate SWPs timing behavior from each other. However, when moving towards parallel execution in many-core processors, the simultaneous accesses to shared hardware and software resources influence the timing behavior of SWPs, defying the purpose of time partitioning to provide isolation among applications. In this paper, we extend the concept of SWP by introducing parallel software partitions (pSWP) specification that describes the behavior of SWPs required when running in a many-core to enable incremental qualification. pSWP are supported by a new hardware feature called guaranteed resource partition (GRP) that defines an execution environment in which SWPs run and that controls interferences in the accesses to shared hardware resources among SWPs such that time composability can be guaranteed.

Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems

“…Clustered designs like those proposed in [23] allow creating independent islands of communication (i.e. clusters) within the wNoC by properly routing packets, which in turn reduces the WCD.…”

“…However, in this case a mechanism is needed to allow inter-cluster communication without jeopardizing the of the affected clusters if they are intended to run real-time tasks. In [23] inter-cluster communication is allowed by using multiple VCs. This approach proposes the use of two VC: one for intra-cluster and another one for inter-cluster communication assuming the amount of inter-cluster communication is a known parameter at system integration.…”

Improving Performance Guarantees in Wormhole Mesh NoC Designs

“…We also evaluate W aW +W aP using 3D path planning (3DPP), an industrial avionics parallel application provided by Honeywell [16]. 3DPP uses 16 cores to guide an aircraft through the obstacle map represented as a 3D matrix.…”

“…We use EEMBC [20] autobench and an avionics realtime parallel application provided by Honeywell [16]. We show that our design significantly decreases WCET estimates for the parallel application by a factor of 4.8× to 9.5× depending on the number of flits per packet.…”

Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors

“…: TDMA or UBD in buses [23]; partitioning for caches [23]; real-time aware controllers for memory [3], [25]. Those solutions simplify timing analysis as contention effects are nullified when the hardware design eliminates contention interference by construction or easily determined when hardware features bound contention interference [22]. Solutions of this kind ultimately enable the use of the two-step analysis process inherited from the singlecore practice.…”