pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems

J. Emerg. Technol. Comput. Syst.

et al. 2019

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Wormhole-based NoCs (wNoCs) are widely accepted in high-performance domains as the most appropriate solution to interconnect an increasing number of cores in the chip. However, wNoCs suitability in the context of critical real-time applications has not been demonstrated yet. In this paper, in the context of probabilistic timing analysis (PTA), we propose a PTA-compatible wNoC design that provides tight timecomposable contention bounds. The proposed wNoC design builds on PTA ability to reason in probabilistic terms about hardware events impacting execution time (e.g. wNoC contention), discarding those sequences of events occurring with a negligible low probability. This allows our wNoC design to deliver improved guaranteed performance w.r.t. conventional time-deterministic setups. Our results show that performance guarantees of applications running on top of probabilistic wNoC designs improve by 40% and 93% on average for 4x4 and 6x6 wNoC setups, respectively.

Section: Reducing Contention In Probabilistic Wnocsmentioning

confidence: 67%

“…TDMA-based buses have also been proven amenable for MBPTA by padding execution time measurements conveniently [28]. A tree NoC implementing wormhole routers with random arbitration and intended for all-to-one communication has also been shown to be amenable for MBPTA [39]. However, trees do not fit well all-to-all communication.…”

Section: Bounds Computationmentioning

confidence: 99%

Time-Randomized Wormhole NoCs for Critical Applications

J. Emerg. Technol. Comput. Syst.

et al. 2019

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“…In the case of probabilistic wNoCs, requests experience the actual contention of the worst-case scenario modeled at analysis, which is enforced not to be exceeded during operation. Therefore, decreasing maximum contention by design opens the door to obtaining lower WCET estimates with probabilistic wNoCs, as already shown for tree wNoCs [23].…”

Section: B Reducing Contention In Probabilistic Wnocsmentioning

confidence: 67%

“…TDMA-based buses have also been proven amenable for MBPTA by padding execution time measurements conveniently [17]. A tree NoC implementing wormhole routers with random arbitration and intended for all-to-one communication has also been shown to be amenable for MBPTA [23]. However, trees do not fit well all-to-all communication.…”

Section: B Performance Evaluationmentioning

confidence: 99%

Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis

2017 Euromicro Conference on Digital System Design (DSD)

et al. 2017

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Abstract-Wormhole-based NoCs (wNoCs) are widely accepted in high-performance domains as the most appropriate solution to interconnect an increasing number of cores in the chip. However, wNoCs suitability in the context of critical real-time applications has not been demonstrated yet. In this paper, in the context of probabilistic timing analysis (PTA), we propose a PTA-compatible wNoC design that provides tight time-composable contention bounds. The proposed wNoC design builds on PTA ability to reason in probabilistic terms about hardware events impacting execution time (e.g. wNoC contention), discarding those sequences of events occurring with a negligible low probability. This allows our wNoC design to deliver improved guaranteed performance. Our results show that WCET estimates of applications running on top of probabilistic wNoCs are reduced by 40% and 75% on average for 4x4 and 6x6 wNoC setups respectively when compared against deterministic wNoCs.

“…As it has been shown in other works in the context of buses or more complex NoCs [13], [22], for the interconnection network this worst-case operation-time conditions can be reproduced by collecting execution times of the TuA under maximum contention scenarios. In our case this can be done enforcing the following conditions: first, contending cores are assumed to always have a request ready to compete with the TuA, but new requests are created only if the TuA has a request ready; and second, contending requests always take the maximum latency, M axL.…”

Section: B Wcet Estimationmentioning

confidence: 96%

Design and implementation of a fair credit-based bandwidth sharing scheme for buses

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

et al. 2017

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Abstract-Fair arbitration in the access to hardware shared resources is fundamental to obtain low worst-case execution time (WCET) estimates in the context of critical real-time systems, for which performance guarantees are essential. Several hardware mechanisms exist for managing arbitration in those resources (buses, memory controllers, etc.). They typically attain fairness in terms of the number of slots each contender (e.g., core) gets granted access to the shared resource. However, those policies may lead to unfair bandwidth allocations for workloads with contenders issuing short requests and contenders issuing long requests. We propose a Credit-Based Arbitration (CBA) mechanism that achieves fairness in the cycles each core is granted access to the resource rather than in the number of granted slots. Furthermore, we implement CBA as part of a LEON3 4-core processor for the Space domain in an FPGA proving the feasibility and good performance characteristics of the design by comparing it against other arbitration schemes.