Enabling compiler flow for embedded VLIW DSP processors with distributed register files

ChenChung-Kai,; TsengLing-Hua,; ChenShih-Chang,; LinYoung-Jia,; YouYi-Ping,; LuChia-Han,; LeeJenq-Kuen,

doi:10.1145/1273444.1254793

Cited by 4 publications

(3 citation statements)

References 8 publications

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“…Programs at PAC-DSP site are compiled with PAC-DSP compiler. The PAC-DSP compiler is developed based on Open64 [25] compiler framework and supports for VLIW DSP processors with distributed register files [26][27][28]. The compilation and simulation flow is shown in Fig.…”

Section: Experimental Configurationsmentioning

confidence: 99%

Compilers for Low Power with Design Patterns on Embedded Multicore Systems

Lin

Kuan

Shih

et al. 2014

J Sign Process Syst

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Minimization of power dissipation can be considered at algorithmic, compiler, architectural, logic, and circuit level. Recent research trends for multicore programming models have come to the direction that parallel design patterns can be a solution to develop multicore applications. As parallel design patterns are with regularity, we view this as a great opportunity to exploit power optimizations in the software layer. In this paper, we investigate compilers for low power with parallel design patterns on embedded multicore systems. We evaluate four major parallel design patterns, Pipe and Filter, MapReduce with Iterator, Puppeteer, and Bulk Synchronous Parallel (BSP) Model. Our work attempts to devise power optimization schemes in compilers by exploiting the opportunities of the recurring patterns of embedded multicore programs. The proposed optimization schemes are rate-based optimization for Pipe and Filter pattern , early-exit power optimization for MapReduce with Iterator pattern, power aware mapping algorithm for Puppeteer pattern, and multi-phases power gating scheme for BSP pattern. In our experiments, real world multicore applications are evaluated on a multicore power simulator. Significant power reductions are observed from the experimental results. Therefore, we present a direction for power optimizations that one can further

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Section: Experimental Configurationsmentioning

confidence: 99%

Compilers for Low Power with Design Patterns on Embedded Multicore Systems

Lin

Kuan

Shih

et al. 2014

J Sign Process Syst

View full text Add to dashboard Cite

show abstract

“…The model was used to guide data flow analysis so as to improve the performance. Moreover, other optimizations such as software pipelining [30], loop nest optimization, and subword optimization have also been improved for the processor.…”

Section: Platform Infrastructurementioning

confidence: 99%

Achieving spilling-friendly register file assignment for highly distributed register files

Shih

et al. 2014

J Supercomput

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Distributed register file architectures divide registers into multiple sets, and it follows that the register files could be small. This can increase the frequency of spilling if register allocation encounters high register pressure, which will reduce the performance. That is, there is extra spilling to handle the pressure and results in performance decline. One of the factors that can produce high pressure is improper register file assignment. Register file assignment is a phase that assigns virtual registers to suitable register files and avoids communication costs. To reduce spilling in the phase of register file assignment, this paper proposes the SPIlling-FRiendly (SPIFR) method, which attempts to improve spilling by estimating the spilling cost from two aspects: assignment and spilling. We used MiBench and EEMBC benchmarks in experiments performed with the Open64-based compiler and a cycle-accurate instruction set simulator. The MiBench experimental results show that the SPIFR method improved the average cycle counts of the benchmarks by 6.0 %. For the kernels of the benchmarks, the method improved the average cycle counts by 20.5 % and reduced the average spilling ratio by 19.0 %. The results on the EEMBC benchmarks indicate that the method improved the cycle counts with the average speedup of 7.0 %, the speedup average of the kernel functions was 11.3 %, and the average reduction in the spilling ratio was 11.7 %, respectively. We conclude that the SPIFR method can reduce spilling and increase the performance.

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“…The PACDSP compiler [14,15] is built based on the open research compiler (ORC) [16], an open source compiler infrastructure that contains various optimizations for high-performance EPIC/VLIW architectures. The ORC frontend helps to generate the intermediate representation, WHIRL, with five representation levels from "very high" to "very low", where various targetindependent optimizations are performed, such as control flow optimization, extended basic block (peephole) optimization, integrated global/local scheduling, and loop transformation at the "very low" level.…”

Section: Software Development Toolsmentioning

confidence: 99%

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools

Chang

Lin

et al. 2010

J Sign Process Syst

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In order to develop a low-power and highperformance SoC platform for multimedia applications, the Parallel Architecture Core (PAC) project was initiated in Taiwan in 2003. AVLIW digital signal processor (PACDSP) has been developed from a proprietary instruction set with multimedia-rich instructions, a complexity-effective microarchitecture with an innovative distributed & ping-pong register organization and variable-length VLIW encoding, to a highly-configurable soft IP with several successful silicon implementations. A complete toolchain with an optimizing C compiler has also been developed for PACDSP. A dualcore PAC SoC has been designed and fabricated, which consists of a PACDSP core, an ARM9 core, scratchpad memories, and various on-chip peripherals, to demonstrate the outstanding performance and energy efficiency for multimedia processing such as the real-time H.264 codec. The first part of the two introductory papers of PAC describes the hardware architecture of the PACDSP core, its software development tools, and the PAC SoC with dynamic voltage and frequency scaling (DVFS).

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Enabling compiler flow for embedded VLIW DSP processors with distributed register files

Cited by 4 publications

References 8 publications

Compilers for Low Power with Design Patterns on Embedded Multicore Systems

Compilers for Low Power with Design Patterns on Embedded Multicore Systems

Achieving spilling-friendly register file assignment for highly distributed register files

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools

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