Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture &amp; Software Development Tools

Chang, David; Lin, Tay-Jyi; Wu, Chung-Ju; Lee, Jenq-Kuen; Chu, Yuan-Hua; Wu, An-Yeu

doi:10.1007/s11265-010-0470-0

Cited by 15 publications

(5 citation statements)

References 11 publications

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“…At last, these programs are evaluated on PACDSP with a cycle‐accurate instruction set simulator. They are also verified on real hardware platforms to ensure correctness and demonstrate performance. Performance numbers we obtained for DSPstone and H.264 kernels are presented in Figure , where performance numbers are shown in speedups over the original programs compiled with the current best compiler level, O2.…”

Section: Experiments and Discussionmentioning

confidence: 99%

“…In this paper, we focus on a VLIW DSP processor, which features novel distributed register designs. The target DSP processor, known as Parallel Architecture Core (PAC) DSP, is a 32‐bit five‐way VLIW DSP processor developed by ITRI Taiwan to serve as SIMD engines in multicore SoC platforms . PACDSP features a clustered architecture with distinctively banked register files whose port access is highly restricted.…”

Section: Introductionmentioning

confidence: 99%

“…The private register files include AC register files for ALUs, A register files for LSUs and R for the scalar unit. To facilitate data sharing between functional units in a cluster, two global files, known as ping‐pong register files , are provided to serve as temporary storage for data sharing and exchanging. To reduce more access ports, the global register files are divided into banks, each of which has restricted port access that only provides exclusive read and exclusive write per cycle.…”

Section: Introductionmentioning

confidence: 99%

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Compiler supports for VLIW DSP processors with SIMD intrinsics

Kuan

Lee

2011

Concurrency and Computation

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SUMMARYTo sustain growing multimedia workload, modern digital signal processing (DSP) processors are commonly equipped with subword instructions to accelerate signal processing. Besides subword, functional units of very long instruction word (VLIW) DSP processors can also be employed to process multiple data streams in parallel. However, because of power and area concerns, many embedded VLIW DSP processors adopt distributed register files to reduce read/write ports and wire connection by privatizing register files for clusters and even for functional units. The distributed design presents great challenges to compilers in distributing single instruction, multiple data (SIMD) workload to functional units. In this paper, we address the issue in supporting SIMD parallelism on VLIW DSP processors with subword instructions and distributed register files. Currently, industrial practices have adopted intrinsics that enable developers to utilize hardware resources and compete with hand-coded assembly in performance. However, it is still an open issue to provide such a solution for VLIW DSP processors with distributed register files. In this work, we provide SIMD intrinsics to allow programmers to write highly optimized codes by following given programming guides. In addition, an enhanced register allocation scheme and data replication optimizations are devised to enable efficient code generation. In our experiments, DSPstone benchmark and a set of H.264 kernels are used to evaluate the proposed programming and optimization schemes. The result shows that by combining SIMD intrinsics and compiler optimizations, one is able to obtain remarkable performance improvements, speedups of 2.9 and 3.5 for DSPstone and H.264 kernels, respectively.

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Section: Experiments and Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Compiler supports for VLIW DSP processors with SIMD intrinsics

Kuan

Lee

2011

Concurrency and Computation

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“…To achieve this goal, we proposed a message-passing library, called MSG, for inter-core communications on the x86 platform, the Cell platform [4] and the PAC Duo platform [5], [6]. We first divided the communication library into three layers and designed each layer to achieve different goals.…”

Section: Introductionmentioning

confidence: 99%

On the Portability and Performance of Message-Passing Programs on Embedded Multicore Platforms

Hung

Chiu

et al. 2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

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Recently, embedded multicore platforms have become popular, but software development for such platforms has been very challenging. While message-passing is a popular programming model for parallel applications, it is not adequately supported on the current embedded multicore platforms. Similar to the situations in '80s~'90s, applications are hardly portable across parallel computers before the advent of MPI. Unfortunately, MPI is too big for most embedded platforms of today. Moreover, the message-passing functions need to utilize the architectural features to offer optimized performance, but such platform-specific optimizations often hurt the portability. This paper addresses the portability and performance issues by designing a new message-passing library with a three-layer modular design. The top two layers are mostly platform-independent, and the bottom layer enables platform-specific optimizations. We discuss the performance issues in the paper and evaluate the issues with experimental results.Index Terms-embedded systems, multicore, performance, message-passing, and portability I. IEEE 26th International Parallel and Distributed Processing Symposium Workshops978-0-7695-4676-6/12 $26.00

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“…Likewise, the PAC project executed by ITRI [8] in Taiwan provides the alternative solution. The first part [9] of these two introductory papers has presented the development results of hardware architecture and toolchains of the PAC SoC. The hardware architecture resolves several specializations, such as clustered VLIW architecture with simple inter-cluster communication mechanism, complexity-reduced distributed and ping-pong register file, efficient variable-length VLIW instruction encoding architecture, and DVFS capability.…”

Section: Introductionmentioning

confidence: 99%

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part II: Application Programming

Chen

Liu

Yang

et al. 2010

J Sign Process Syst

Self Cite

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Two representative multimedia applications-AAC and H.264/AVC decoders on the parallel architecture core (PAC) SoC are introduced in the second part of the two introductory papers. The applications have been programmed on the PACDSP core and the PAC SoC to demonstrate the high-performance, low-power DSP computations and the effectiveness of the dynamic voltage and frequency scaling (DVFS) capability on the heterogeneous multicore SoC. First, techniques to exploit data-and instruction-level parallelisms existing in the application kernels are described for performance optimizations on the clustered VLIW architecture of PACDSP with the distributed register organization. Next, two variation techniques of asymmetric programming model are introduced by examples of decoders. Then, the energy efficiency of the programmable multimedia SoC is demonstrated using an innovative power-aware H.264/AVC decoder. Finally, a DVFS-aware framework for soft real-time video playback is provided by extending the power-aware decoding scheme. The work provides practical references of realizing multimedia applications on PAC SoC suitable for richfunction and resource constraint portable devices.

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Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools

Cited by 15 publications

References 11 publications

Compiler supports for VLIW DSP processors with SIMD intrinsics

Compiler supports for VLIW DSP processors with SIMD intrinsics

On the Portability and Performance of Message-Passing Programs on Embedded Multicore Platforms

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part II: Application Programming

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