Compiler supports for VLIW DSP processors with SIMD intrinsics

Abstract

SUMMARYTo sustain growing multimedia workload, modern digital signal processing (DSP) processors are commonly equipped with subword instructions to accelerate signal processing. Besides subword, functional units of very long instruction word (VLIW) DSP processors can also be employed to process multiple data streams in parallel. However, because of power and area concerns, many embedded VLIW DSP processors adopt distributed register files to reduce read/write ports and wire connection by privatizing register files for clusters and even for functional units. The distributed design presents great challenges to compilers in distributing single instruction, multiple data (SIMD) workload to functional units. In this paper, we address the issue in supporting SIMD parallelism on VLIW DSP processors with subword instructions and distributed register files. Currently, industrial practices have adopted intrinsics that enable developers to utilize hardware resources and compete with hand-coded assembly in performance. However, it is still an open issue to provide such a solution for VLIW DSP processors with distributed register files. In this work, we provide SIMD intrinsics to allow programmers to write highly optimized codes by following given programming guides. In addition, an enhanced register allocation scheme and data replication optimizations are devised to enable efficient code generation. In our experiments, DSPstone benchmark and a set of H.264 kernels are used to evaluate the proposed programming and optimization schemes. The result shows that by combining SIMD intrinsics and compiler optimizations, one is able to obtain remarkable performance improvements, speedups of 2.9 and 3.5 for DSPstone and H.264 kernels, respectively.

The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems

“…Therefore, compared with compiler option O0, there is some increase in power consumption of the PAC-DSP core under compiler options O2 and O2-with-SIMD-intrinsics. Also, the PAC-DSP compiler has SIMD intrinsic functions support for parallel data processing via source-level operations of SIMD instructions [Kuan and Lee 2012] (SIMD intrinsics are described in the next paragraph). Figure 10 illustrates the normalized energy consumption (bar charts) and performance improvement (line graphs) for different compiler optimization levels.…”

Special Issue: Compilers for Parallel Computing (CPC 2010)

“…This genericity results in many expensive dynamic checks at runtime, which their new system handles using adaptive optimization. Frequently executed program parts are specialized at runtime, using a full‐fledged optimizing compiler running on a dedicated core.Experimental results show good speedups with runtime specialization at minimal overhead. Compiler supports for VLIW DSP processors with SIMD intrinsics by Chi‐Bang Kuan and Jenq Kuen Lee considers the difficult problem of programming a processor with a distributed register file. They propose a set of SIMD intrinsics and programming guidelines along with a novel register allocation scheme that allows generation of efficient code without requiring hand‐written assembly code.Using these intrinsics, the authors parallelized two DSP benchmark sets with impressive results.…”

“…Compiler supports for VLIW DSP processors with SIMD intrinsics by Chi‐Bang Kuan and Jenq Kuen Lee considers the difficult problem of programming a processor with a distributed register file. They propose a set of SIMD intrinsics and programming guidelines along with a novel register allocation scheme that allows generation of efficient code without requiring hand‐written assembly code.…”