The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems

Lin, Cheng-Yen; Huang, Chung-Wen; Kuan, Chung‐Ming; Huang, Shi-Yu; Lee, Jenq-Kuen

doi:10.1145/2699834

Cited by 2 publications

(1 citation statement)

References 51 publications

(36 reference statements)

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“…In this work, on the other hand, we propose a methodology to automatically generate the CPF power specification from a high-level model just like an HLS tool generates the RTL from a behavioral description. Benini et al [2001] and Lin et al [2015] suggest various energy optimizations starting from software down to circuit-level for electronic systems. Their strategy starts from power optimizations at system-level including energy-aware task scheduling, hardware/software partitioning, power aware architectures using dynamic power management (DPM) policies and code morphing.…”

Section: Related Workmentioning

confidence: 99%

LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow

Qamar

Muslim

Iqbal

et al. 2017

Microprocessors and Microsystems

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The abstraction level for digital designs is rising from Register Transfer Level (RTL) to algorithmic untimed or transaction-based, followed by an automated high level synthesis (HLS) flow. However, it is still a significant challenge for chip architects and designers to describe low-power design decisions at the system level. Nowadays, low power design techniques for digital blocks are applied at RTL and there exists no commercial tool or methodology that can automatically derive the power intent from the system level description. The process requires considerable amount of human intervention and various lower-level details that are needed to implement low power schemes at RTL. This research aims to integrate low power techniques, specifically Power Shut-Off (PSO), within a model based hardware flow and to derive an automated Low Power-High Level Synthesis (LP-HLS) methodology. The methodology aims at minimizing the design effort for low power design by deriving low-level power intent automatically for model-based designs, while using high level synthesis to achieve a broad set of target system implementations. All the information that is needed to implement low power techniques is automatically derived from the systemlevel design using a set of pragmas and a directives file. To illustrate the methodology, three model designs, ranging from simple designs to medium complexity hardware accelerators, are considered. Finally, the power saving results for the design scenarios validate the effectiveness of our LP-HLS methodology. • Hardware~Best practices for EDA • Hardware~Software tools for EDA • Hardware~Hardware description languages and compilation • Hardware~Modeling and parameter extractionAdditional Key Words and Phrases: Hardware accelerators, HLS, RTL, design space exploration, common power format, low power designs, design automation.

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Section: Related Workmentioning

confidence: 99%

LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow

Qamar

Muslim

Iqbal

et al. 2017

Microprocessors and Microsystems

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The Support of MISRA C++ Analyzer for Reliability of Embedded Systems

Lin,

Chu,

Chang

et al. 2023

ACM Trans. Cyber-Phys. Syst.

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Cyber-Physical Systems (CPS) are increasingly used in many complex applications, such as autonomous delivery drones, the automotive CPS design, power grid control systems, and medical robotics. However, existing programming languages lack certain design patterns for CPS designs, including temporal semantics and concurrency models. Future research directions may involve programming language extensions to support CPS designs. On the other hand, JSF++, MISRA, and MISRA C++ are providing specifications intended to increase the reliability of safety-critical systems. This article also describes the development of rule checkers based on the MISRA C++ specification using the Clang open-source tool, which allows for the annotation of code and the easy extension of the MISRA C++ specification to other programming languages and systems. This is potentially useful for future CPS language research extensions to work with reliability software specifications using the Clang tool. Experiments were performed using key C++ benchmarks to validate our method in comparison with the well-known Coverity commercial tool. We illustrate key rules related to class, inheritance, template, overloading, and exception handling. Open-source benchmarks that violate the rules detected by our checkers are also illustrated. A random graph generator is further used to generate diamond case with multiple inheritance testdata for our software validations. The experimental results demonstrate that our method can provide information that is more detailed than that obtained using Coverity for nine open-source C++ benchmarks. Since the Clang tool is widely used, it will further allow developers to annotate their own extensions.

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The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems

Cited by 2 publications

References 51 publications

LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow

LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow

The Support of MISRA C++ Analyzer for Reliability of Embedded Systems

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