Empirical Characteristics and Extraction of Overall Variations for 65-nm MOSFETs and Beyond

Kanno, M.; Shibuya, Atsushi; Matsumura, M.; Tamura, Kenichi; Tsuno, H.; Mori, Shigeo; Fukuzaki, Yuzo; Gocho, T.; Ansai, Hisahiro; Nishida, Naoki

doi:10.1109/vlsit.2007.4339738

Cited by 31 publications

(12 citation statements)

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“…Therefore, the process variation of advanced process technology nodes greatly increases and becomes a critical factor in both IC design and manufacturing [1]. To design and manufacture in the presence of process variation, many research efforts have been focused on the areas of measurement, analysis, and modeling of variation during the past decade [2]- [9], [12]. Furthermore, modeling and design for manufacturing (DFM) of increasingly complex process technologies incorporating process features such as stressed contact etch-stop layers, SiGe source/drain [9], stress memorization technique [11], and so forth requires a much larger range of test structures and larger data volume to accurately characterize the layout-dependent effects (LDE) resulting from these process features.…”

Section: Introductionmentioning

confidence: 99%

Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization

Luo

Chao

Tseng

et al. 2014

IEEE Trans. VLSI Syst.

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As process technologies continually advance, process variation has greatly increased and has gradually become one of the most critical factors for IC manufacturing. Furthermore, these increasingly complex processes continue to make greater use of stressors for mobility enhancement, thus requiring large volumes of data for extensive characterization of layoutdependent effects (LDE) for validation of both SPICE models and design for manufacturing. Transistor threshold voltage (V t) is a commonly used parameter both for characterization during process development and for monitoring of volume manufacturing. To adequately quantify local process variation or LDE, V t must be measured for a sufficiently large number of deviceunder-tests (DUTs) to obtain a statistically representative sample population. The number of V t measurements required to obtain such a statistically significant result, however, requires extremely long testing time, especially for array-based test structure designs including thousands of DUTs. In this paper, we present a very fast threshold voltage measurement methodology using an operational amplifier-based source-measure unit test configuration, which greatly improves testing efficiency and accuracy, and is not sensitive to process variation. The proposed test methodology can improve V t testing time by a factor of 5-10 relative to the commonly used binary-search algorithm, and by a factor of ∼2 relative to an optimized interpolation algorithm, and achieves better accuracy (standard deviation of V t = 0.15 mV, versus typical accuracy of ∼ 0.5 mV for the two algorithms mentioned). Furthermore, the layout and configuration of conventional test structures need not be modified to adapt the proposed methodology. The measured results from the most advanced process technology nodes demonstrate the testing efficiency and accuracy of the proposed test structure in characterizing the large number of DUTs required for quantifying process variation or LDEs.

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Section: Introductionmentioning

confidence: 99%

Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization

Luo

Chao

Tseng

et al. 2014

IEEE Trans. VLSI Syst.

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“…ROs can be used to identify possible causes and levels of layout-dependent variability in 90 nm and 45 nm generation circuits [2] [3]. Kanno used ROs to characterize gate-to-active distance to extract layoutdependent systematic variations for the 65nm node [4].…”

Section: Introductionmentioning

confidence: 99%

45nm-generation parameter-specific ring oscillator monitors

Wang

Liu

et al. 2010

SPIE Proceedings

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Experimental results are reported for ring oscillators (ROs) fabricated using 45nm generation CMOS technology and inverter layouts that are designed to identify and quantify sources of circuit performance variation due to gate etch/lithography, gate-to-active misalignment, and CESL-induced stress. The measured RO frequency data show that within-chip variation is negligible in comparison with chip-to-chip variation. Standard-deviation over mean (σ/µ) values among 36 RO instances show a slight channel area dependence of 0.2% versus sqrt(area) -1 . For a typical wafer, 3% RO frequency change due to gate etch/focus variations, 2-3nm overlay error, and a 5% increase by doubling the length of diffusion (LOD) can be measured.

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“…Scaling toward 65 nm and beyond, variability in the delay and power consumption of CMOS devices, circuits, and chips affected by process variations is increased and influences both functional yield and parametric yield [1][2]. The process variations consist of systematic components and random components ( Figure 1).…”

Section: Introductionmentioning

confidence: 99%

OPC to reduce variability of transistor properties

et al. 2007

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Scaling toward 65 nm and beyond, process variations are increased and influences both functional yield and parametric yield. The process variations consist of systematic components and random components. Systematic variations are caused by predictable design and process procedures, therefore systematic variations should be removed from process corner model for LSI design. With the effect of scaling, print images on a wafer shows complicated distortion. The method of calculating distorted transistor properties without slicing into individual rectangular transistors has been previously proposed. Using this calculation method, transistor properties with distortion are able to be calculated, reduction of transistor property variations is expected. Transistor property variations caused by layout dependence could be reduced by using OPC with SPICE for each transistor, however, the calculation time of gate length retarget with SPICE is not realistic. Therefore we have investigated approximation for transistor properties using statistics of gate length distribution and layout parameters, and found that parameter fitting by average and σ of gate length distribution of each transistor is useful. According to the results of application to standard cell libraries using OPC with transistor property estimation, we have achieved that our new OPC reduces threshold voltage and drive current variations greatly without increasing throughput. It is difficult to suppress variation about all properties without area penalty, however, property priority required for each transistor is different. Therefore performance improvement of the whole circuit and chip is possible by the argument of priority between manufacturing engineer and circuit designer or using design intents.

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Empirical Characteristics and Extraction of Overall Variations for 65-nm MOSFETs and Beyond

Cited by 31 publications

References 1 publication

Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization

Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization

45nm-generation parameter-specific ring oscillator monitors

OPC to reduce variability of transistor properties

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