At deep sub-wavelength nodes, it is difficult to transfer accurate mask pattern onto the wafer. However, actual gate pattern is distorted, and timing analysis tools calculates circuit performance on the assumption that the same gate length exists throughout the whole gate width. We calculated the property of the original 2 dimensional distorted transistor by using distribution of gate length. Firstly, in order to evaluate the accuracy of this approach, we have compared them with experimental results that may influence the 65 nm-node design rule. In the conventional method using a rectangular model, results of transistor properties are different from the experimental values, however, results of this approach can reproduce the experimental results. Secondly, this approach is applied to optimization of layout design and OPC. In order to investigate the influence of circuit performance on a layout design and OPC, we calculated the properties (drive current; Ion and leakage current; Ioff) of each transistor contained in standard cell library which is most referred to in a system LSI. We have investigated 2 layouts and 8 OPCs. According to these results, we find out that optimal OPC differs according to the prioritization of Ion and Ioff, whether it is an N-channel or P-channel, and also by layout. Furthermore relaxation of layout decreases variability of Ion caused by defocus. Moreover, since the influence of pattern distortion can be expressed by circuit term such as Ion and Ioff in addition to conventional process terms, it becomes easier for designers to understand manufacturing issues.
Scaling toward 65 nm and beyond, process variations are increased and influences both functional yield and parametric yield. The process variations consist of systematic components and random components. Systematic variations are caused by predictable design and process procedures, therefore systematic variations should be removed from process corner model for LSI design. With the effect of scaling, print images on a wafer shows complicated distortion. The method of calculating distorted transistor properties without slicing into individual rectangular transistors has been previously proposed. Using this calculation method, transistor properties with distortion are able to be calculated, reduction of transistor property variations is expected. Transistor property variations caused by layout dependence could be reduced by using OPC with SPICE for each transistor, however, the calculation time of gate length retarget with SPICE is not realistic. Therefore we have investigated approximation for transistor properties using statistics of gate length distribution and layout parameters, and found that parameter fitting by average and σ of gate length distribution of each transistor is useful. According to the results of application to standard cell libraries using OPC with transistor property estimation, we have achieved that our new OPC reduces threshold voltage and drive current variations greatly without increasing throughput. It is difficult to suppress variation about all properties without area penalty, however, property priority required for each transistor is different. Therefore performance improvement of the whole circuit and chip is possible by the argument of priority between manufacturing engineer and circuit designer or using design intents.
We examined two EPL mask fabrication processes to control precisely image placement (IP) on the EPL masks. One is a wafer process using an electrostatic chuck during an e-beam write and another is a membrane process using a mechanical chuck during the e-beam write. In the wafer process, the global IP is corrected during the e-beam write on the basis of the IP data taken with x-y metrology tool. In the membrane process, the global IP is corrected during the ebeam write on the basis of the data taken with the x-y metrology tool and taken in situ with the e-beam writer. The resist and final global IP (3σ) of the wafer process is 7.2 nm and 10.6 nm. For the average local IP errors (3σ), the local IP of 5.7 nm at the resist step increases to 14.7 nm at the final step due to process-induced distortions. The local IP could be reduced to 6.0 nm by applying the constant scale value to the mask process. In the membrane process, the resist and final global IP (3σ) is 15.3 nm and 17.1 nm. With more detectable alignment marks, it would be possible to improve the global IP. For the average local IP errors (3σ) of the membrane process, the average resist and final local IP are 6.7 and 7.1 nm which shows no PID. The two approaches proved to control IP more accurately than the conventional one.
We present a finite difference frequency domain (FDFD) algorithm for the vector wave equation. Employing covariant formulations, arbitrary curvilinear, non-orthogonal computational grids are mapped onto equidistant Cartesian coordinates. This provides an intrinsic method for a local increase of computational accuracy and application of standard finite difference expressions. As an example this technique is applied to the microwave plasma torch (MPT). It is shown that there is a high field plasma generating region on top of the inner conductor. The interior of this region is of comparably low electrical field strength and supposed to be responsible for the hollow structure of the plasma observed in this type of plasma source.
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