Emerging yield and reliability challenges in nanometer CMOS technologies

Gielen, Georges; Wit, Pieter De; Maricau, Elie; Loeckx, Johan; Martín-Martínez, J.; Kaczer, B.; Groeseneken, G.; Rodrı́guez, R.; Nafrı́a, Montserrat

doi:10.1145/1403375.1403694

Cited by 71 publications

(52 citation statements)

References 36 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Recent work has shown that the threshold voltage shift as a function of time under DC stress (t DC ) is best modeled with the trapping/de-trapping theory [3][4][5][6]:…”

Section: Nbti/pbtimentioning

confidence: 99%

Comprehensive reliability and aging analysis on SRAMs within microprocessor systems

Liu

Chen

Kim

et al. 2015

Microelectronics Reliability

View full text Add to dashboard Cite

a b s t r a c tA framework is proposed to analyze the impact of both Front End of the Line (FEOL) and Back End of the Line (BEOL) wearout mechanisms on memories embedded within state-of-art microprocessors. Our methodology finds the detailed electrical stress and temperature of each SRAM cell within a memory by running a variety of standard benchmarks. Combining the stress/thermal profiles and the wearout models, the performance degradation of SRAM cells for each wearout mechanism is studied. The lifetimes of the SRAM cells are then obtained when the performance metric degrades to a predefined threshold. The proposed work introduces a method to deal with the large volume of SRAM cells whose stress is non-uniform by partitioning the SRAM cells into different stress states, and generates the lifetime distribution of the memory system due to each wearout mechanism by combining the lifetimes of the cells, whose distributions vary with the stress received. Seven wearout mechanisms have been studied, namely, negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), hot carrier injection (HCI), gate oxide breakdown (GOBD), backend dielectric breakdown (BTDDB), electromigration (EM), and stress-induced voiding (SIV).

show abstract

“…Recent work has shown that the threshold voltage shift as a function of time under DC stress (t DC ) is best modeled with the trapping/de-trapping theory [3][4][5][6]:…”

Section: Nbti/pbtimentioning

confidence: 99%

Comprehensive reliability and aging analysis on SRAMs within microprocessor systems

Liu

Chen

Kim

et al. 2015

Microelectronics Reliability

View full text Add to dashboard Cite

show abstract

“…Time-dependent degradation Time-dependent degradation effects will cause a change of the transistor parameters (V T , J, r o ) as a function of time and therefore might turn an initially fully functional circuit into a less or even non-functional circuit over time [2]. This degradation depends on the stress applied to the device, i.e.…”

Section: 2mentioning

confidence: 99%

Design automation towards reliable analog integrated circuits

Gielen¹,

Maricau²,

Wit³

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

View full text Add to dashboard Cite

Reliability is becoming one of the major concerns in designing integrated circuits in nanometer CMOS technologies. Problems related to degradation mechanisms like NBTI or soft breakdown, as well as increased external interference such as caused by crosstalk and EMI, cause timedependent circuit performance degradation. Variability only makes these things more severe. This creates a need for innovative design techniques and design tools that help designers coping with these reliability and variability problems. This tutorial paper gives a brief description of design tools for the efficient analysis and identification of reliability problems in analog circuits, as a first step towards the automated design of guaranteed reliable analog circuits.

show abstract

“…Both NBTI and HC increase exponentially with the stress voltage [2]. Therefore, the effect of time-varying stress signals must be included in the model to assure a sufficiently accurate degradation calculation.…”

Section: Degradation Modelsmentioning

confidence: 99%

“…According to the ITRS roadmap both analog and digital ICs start to suffer from die-level reliability phenomena, e.g. Negative Bias Temperature Instability (NBTI) and Hot Carrier degradation (HC) [1], [2]. Statistical circuit analysis through accelerated stress testing (i.e.…”

Section: Introductionmentioning

confidence: 99%

Efficient reliability simulation of analog ICs including variability and time-varying stress

Maricau

Gielen

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

Self Cite

View full text Add to dashboard Cite

Aggressive scaling to nanometer CMOS technologies causes both analog and digital circuit parameters to degrade over time due to die-level stress effects (i.e. NBTI, HCI, TDDB, etc). In addition, failure-time dispersion increases due to increasing process variability. In this paper an innovative methodology to simulate analog circuit reliability is presented. Advantages over current state of the art reliability simulators include, among others, the possibility to estimate the impact of variability and the ability to account for the effects of complex time-varying stress signals. Results show that taking time-varying stress signals into account provides circuit reliability information not visible with classic DC-only reliability simulators. Also, variability-aware reliability simulation results indicate a significant percentage of early circuit failures compared to failure-time results based on nominal design only.

show abstract

Emerging yield and reliability challenges in nanometer CMOS technologies

Cited by 71 publications

References 36 publications

Comprehensive reliability and aging analysis on SRAMs within microprocessor systems

Comprehensive reliability and aging analysis on SRAMs within microprocessor systems

Design automation towards reliable analog integrated circuits

Efficient reliability simulation of analog ICs including variability and time-varying stress

Contact Info

Product

Resources

About