Comprehensive reliability and aging analysis on SRAMs within microprocessor systems

Liu, Taizhi; Chen, Chang-Chih; Kim, Woongrae; Milor, Linda

doi:10.1016/j.microrel.2015.06.078

Cited by 15 publications

(3 citation statements)

References 24 publications

(28 reference statements)

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“…Zhu et al (2017a) presented a systematic study on heterogeneous processors with power caps considered. Moreover, low-power, reliability, and performance/watt ratio optimization are also crucial considerations (Branover et al 2012;Zhu et al 2017a;Liu et al 2015Liu et al , 2016. Different from these research, our study focuses on sparse matrix and graph kernels.…”

Section: Performance Analysis For Coupled Heterogeneous Processorsmentioning

confidence: 99%

Performance evaluation and analysis of sparse matrix and graph kernels on heterogeneous processors

et al. 2019

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Heterogeneous processors integrate very distinct compute resources such as CPUs and GPUs into the same chip, thus can exploit the advantages and avoid disadvantages of those compute units. We in this work evaluate and analyze eight sparse matrix and graph kernels on an AMD CPU-GPU heterogeneous processor by using 956 sparse matrices. Five characteristics, i.e., load balancing, indirect addressing, memory reallocation, atomic operations, and dynamic characteristics are our major considerations. The experimental results show that although the CPU and GPU parts access the same DRAM, very different performance behaviors are observed. For example, though the GPU part in general outperforms the CPU part, it cannot achieve the best performance in all cases given by the CPU part. Moreover, the bandwidth utilization of atomic operations on heterogeneous processors can be much higher than a high-end discrete GPU.

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Section: Performance Analysis For Coupled Heterogeneous Processorsmentioning

confidence: 99%

Performance evaluation and analysis of sparse matrix and graph kernels on heterogeneous processors

et al. 2019

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“…In this chapter, we used the predictive HCI lifetime models for long-term performance-degradation simulations, where the Δ V th degradations due to HCI during stress time are modeled as [25][26][27] (4) where t stress is the stress time, r trans is the frequency-dependent transition rate, t trans is the transition time, and A HCI is a constant that depends on the inversion charge, the trap generation energy, the hot electron mean free path, and other process-dependent factors [28,29].…”

Section: Hcimentioning

confidence: 99%

Reliability and Aging Analysis on SRAMs Within Microprocessor Systems

Liu¹,

Chen²,

Milor³

2018

Dependability Engineering

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The majority of transistors in a modern microprocessor are used to implement static random access memories (SRAM). Therefore, it is important to analyze the reliability of SRAM blocks. During the SRAM design, it is important to build in design margins to achieve an adequate lifetime. The two main wearout mechanisms that increase a transistor's threshold voltage are bias temperature instability (BTI) and hot carrier injections (HCI). BTI and HCI can degrade transistors' driving strength and further weaken circuit performance. In a microprocessor, first-level (L1) caches are frequently accessed, which make it especially vulnerable to BTI and HCI. In this chapter, the cache lifetimes due to BTI and HCI are studied for different cache configurations, namely, cache size, associativity, cache line size, and replacement algorithm. To give a case study, the failure probability (reliability) and the hit rate (performance) of the L1 cache in a LEON3 microprocessor are analyzed, while the microprocessor is running a set of benchmarks. Essential insights can be provided from our results to give better performance-reliability tradeoffs for cache designers.

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“…Hence, a code symbol with availability t can be locally repaired even there are t − 1 node failures. Many recent works on LRCs focused on the study of availability-(r, t), which is the key to fault-tolerance in coding theory, system reliability and computation architecture [10][11][12]. In this paper, our works focus on single-parity LRCs with t available disjoint repairable groups (availability t ≥ 1).…”

Section: Introductionmentioning

confidence: 99%

On the Single-Parity Locally Repairable Codes with Multiple Repairable Groups

Liu

Xia

2018

Information

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Locally repairable codes (LRCs) are a new family of erasure codes used in distributed storage systems which have attracted a great deal of interest in recent years. For an [ n , k , d ] linear code, if a code symbol can be repaired by t disjoint groups of other code symbols, where each group contains at most r code symbols, it is said to have availability- ( r , t ) . Single-parity LRCs are LRCs with a constraint that each repairable group contains exactly one parity symbol. For an [ n , k , d ] single-parity LRC with availability- ( r , t ) for the information symbols (single-parity LRCs), the minimum distance satisfies d ≤ n - k - ⌈ k t / r ⌉ + t + 1 . In this paper, we focus on the study of single-parity LRCs with availability- ( r , t ) for information symbols. Based on the standard form of generator matrices, we present a novel characterization of single-parity LRCs with availability t ≥ 1 . Then, a simple and straightforward proof for the Singleton-type bound is given based on the new characterization. Some necessary conditions for optimal single-parity LRCs with availability t ≥ 1 are obtained, which might provide some guidelines for optimal coding constructions.

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Comprehensive reliability and aging analysis on SRAMs within microprocessor systems

Cited by 15 publications

References 24 publications

Performance evaluation and analysis of sparse matrix and graph kernels on heterogeneous processors

Performance evaluation and analysis of sparse matrix and graph kernels on heterogeneous processors

Reliability and Aging Analysis on SRAMs Within Microprocessor Systems

On the Single-Parity Locally Repairable Codes with Multiple Repairable Groups

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