Embedded Analog CMOS Neural Network inside high speed camera

Abstract

Analog VLSI on-chip learning Neural Networks represent a mature technology for a large number of applications involving industrial as well as consumer appliances. This is particularly the case when low power consumption, small size and/or very high speed are required. This approach exploits the computational features of Neural Networks, the implementation efficiency of analog VLSI circuits and the adaptation capabilities of the on-chip learning feedback schema. High-speed video cameras are powerful tools for investigating for instance the biomechanics analysis or the movements of mechanical parts in manufacturing processes. In the past years, the use of CMOS sensors instead of CCDs has enabled the development of high-speed video cameras offering digital outputs, readout flexibility, and lower manufacturing costs. In this paper, we propose a high-speed smart camera based on a CMOS sensor with embedded Analog Neural Network.

Best Practices for Designing and Training Neural Networks Subjected to Random Variations

“…Inter-device variations change the performance of each ANN, resulting in unpredictable behavior and reduced accuracy. Some have attempted training each ANN individually to fine-tune the network so it learns to handle the unknown changes (i.e., on-chip training, chip-in-the-loop training), but this leads to a variety of costs in terms of manufacturing time, high-precision design, and non-transferrable, uninterpretable models [7], [11], [14]- [22]. The work covered in this paper is another step on the path to developing a train-once-programall method that achieves desirable levels of accuracy while minimizing inter-device performance variation.…”

Design Analog Layout Using Schematic-Driven EDA Tools

“…The Circuit neural network unit cell consists of (i)multipliers, (ii)OP-AMP, and (iii)sigmoid [1]. Multiplier circuit is used to do the calculations between input and weight given.…”

“…This sigmoid function to generate activation functions for neurons. At the beginning of the design of neural networks that are based on a single architecture perceptron and Figure 1 as we proposed to redsign [1][2]. …”

“…So an analog design could match well between schematic and layout, it can use the Schematic-Driven Layout (SDL) of EDA tools as a tool. This paper focus to make redesign layout of the circuit multiplier as case study that is part of a circuit analog neural networks which become current research [1] [2]. Problems in making the layout redesign for this circuit is how to redisgn the layout easily, simple, quickly, and reduce or optimize layout area (size) then before [2] without having to do a full custum design.…”

“…DESIGN FLOW There are 9 phases of design flow, For 4 steps first is logic level and 5 steps second is physical level [5]. Circuit schematic of a multiplier previously been made and through the simulation phase [1] [2]. Making the multiplier circuit schematic design entry using the software "Design ArchitectIC" which is part of ICFLow.…”