Design Analog Layout Using Schematic-Driven EDA Tools

Harahap, Robby Kurniawan; Prasetyo, Eri; Heruseto, Brahmantyo; Afandi, Hamzah

doi:10.2991/iceem-15.2015.17

Cited by 2 publications

(4 citation statements)

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“…Additionally, reference [9] highlights that the primary functionality of IC layout tools revolves around drawing the physical IC layout. Although there exists the Schematic Driven Layout (SDL) feature, it merely facilitates the straightforward conversion of circuit elements from the schematic diagram to the IC layout without offering any Design for Manufacturing (DFM) effects or alerts to IC designers regarding DFM-related concerns.…”

Section: Methods Of a New Design Processmentioning

confidence: 99%

“…IC design and layouts in advanced manufacturing processes must comply with relevant procedures in PDK libraries. In the current era in which PDKs and interoperable PDK tools are often used in IC design, various layout approaches have been proposed, such as the use of schematic-driven electronic design automation tools [9,12] and schematic-driven layout (SDL) flowcharts. Regarding commercially available design tools, the LakerOA and CCSE IC layout tools developed by Synopsys feature SDL functions and can be used in combination with a PDK and the interoperable PDK libraries provided by foundries.…”

Section: Algorithm and Automationmentioning

confidence: 99%

“…In our research, we utilized the Synopsys LakerOA tool [9]. Leveraging the SDL (Schematic-Driven Layout) concept from [9], we connected the schematic and layout designs.…”

Section: Algorithm and Automationmentioning

confidence: 99%

“…In our research, we utilized the Synopsys LakerOA tool [9]. Leveraging the SDL (Schematic-Driven Layout) concept from [9], we connected the schematic and layout designs. SDL enables interactive communication between the schematic and layout, ensuring that all layout components generated by SDL contain information from the circuit schematic, such as NET/NOTE data.…”

Section: Algorithm and Automationmentioning

confidence: 99%

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Mitigating the Effects of Design for Manufacturability on Design Iteration Cycles in Advanced Integrated Circuit Design

Wu,

2023

Electronics

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In integrated circuit (IC) design for advanced manufacturing processes, iterative improvement processes are an approach commonly used for improving design quality, particularly for low-energy, high-frequency circuits. Layout-dependent effects (LDEs) affect IC design and fabrication, resulting in differences in circuit functionality and performance in presimulation versus postsimulation. These differences can greatly increase the length of design iteration cycles. Foundries have attempted to accelerate the iterative design process by providing process design kit libraries to IC designers. However, these kits can neither fully mitigate the negative affect of LDEs on design for manufacturability (DFM) nor eliminate the difference between presimulation and postsimulation results. To address this problem, this study proposed a novel algorithm-based design process in which an IC designer can use layout parasitic extraction to extract the DFM parameters of all components in a circuit prior to the routing process; these parameters include netlists that describe the internal connectivity of components as well as their interconnectivity with other components. Accordingly, the IC designer can determine the effects of DFM parameters on the circuit and modify them in advance if necessary. When the LDEs generated by device placement have been confirmed to not affect circuit properties, physical verification of the routing of metal wires in the IC layout can be performed. In this verification, postsimulations only need to focus on problems regarding the wire loading and timing effects of metal routing. The proposed design process is useful for mitigating LDEs in IC design and considerably reduces the time required for iterative improvement processes. Specifically, this study provides a method of enhancing design iteration cycles and provides guidelines for analyzing factors that hinder IC device functionality and performance. In sum, various problems can be resolved by separately extracting the DFM parameters associated with LDEs and parasitic parameters associated with routing.

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Section: Methods Of a New Design Processmentioning

confidence: 99%

Section: Algorithm and Automationmentioning

confidence: 99%

“…In our research, we utilized the Synopsys LakerOA tool [9]. Leveraging the SDL (Schematic-Driven Layout) concept from [9], we connected the schematic and layout designs.…”

Section: Algorithm and Automationmentioning

confidence: 99%

Section: Algorithm and Automationmentioning

confidence: 99%

See 2 more Smart Citations