Elimination of GeO2 and Ge3N4 interfacial transition regions and defects at n-type Ge interfaces: A pathway for formation of n-MOS devices on Ge substrates

Lucovsky, G.; Lee, S.; Long, J. P.; Seo, Hyungtak; Lüning, J.

doi:10.1016/j.apsusc.2008.03.157

Cited by 26 publications

(17 citation statements)

References 16 publications

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“…The interfacial nitridation is superficial and extends over about three molecular layers suggesting that elimination of Ge-N in the N K edge spectrum should decrease significantly after an annealing at 650°C. 6,7,17 This is indeed the case for the 1.5 nm thick HfO 2 film on Ge͑100͒ in Fig. 3͑a͒ where Ge-N bonding is evident in the asdeposited film, and the film after being annealed at 600 and 650°C.…”

Section: B Meis: Elimination Of Interfacial Ge-n Bonding During Postmentioning

confidence: 66%

“…HfO 2 films were deposited by 300°C remote plasmaenhanced chemical-vapor deposition onto remote plasmanitrided Ge substrates, 6,7 and compared to the same dielectrics deposited onto Si substrates with ϳ0.6-0.8 nm thick SiON interfacial layers. 8,9 Prior to plasma processing native oxides were removed by wet chemistry techniques that have been optimized for Ge substrates using visible/vacuum ultraviolet spectroscopic ellipsometry, and are qualitatively different than conventional wet chemical processing for Si substrates; i.e., they are generally less acidic in nature.…”

Section: Methodsmentioning

confidence: 99%

“…Previously reported studies from our group have suggested that the increased levels of trapping at Ge substrates which are negatively biased results from an interfacial gate stack alignment in which the conduction band offset energy between the Ge substrate and a native Ge dielectric ITR is less than that of the conduction band offset energy ͑CBOE͒ between a Hf-or Zr-based high-K dielectric and the Ge substrate. 6 This arrangement can lead to the formation of a potential well that localizes and confines electrons at the interface, and thereby accounts for high interfacial densities of negative trapped charge.…”

Section: Introductionmentioning

confidence: 99%

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Predeposition plasma nitridation process applied to Ge substrates to passivate interfaces between crystalline-Ge substrates and Hf-based high-K dielectrics

Lucovsky

Long

Chung

et al. 2009

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Interfaces between crystalline-Si and high-K Hf-based oxide gate dielectrics have a lower-K interfacial transition region (ITR), generally 0.6–0.8nm SiON, which prevents reactions between Si and Hf precursors used in film deposition. These ITRs contribute ∼0.35nm to the equivalent oxide thickness limiting aggressive scaling. This article addresses Hf-based high-K gate dielectrics for devices on crystalline Ge substrates. The band gaps of GeO2 and Ge3N4 are reduced with respect to their Si counterparts, and as such may contribute to increased levels of interfacial defect states. A novel processing sequence is presented for (i) depositing HfO2 and Hf Si oxynitrides (HFSiON) onto N-passivated Ge(111) and Ge(100), and subsequently (ii) removing Ge–N interfacial bonding during 800°C thermal annealing in Ar. Near edge x-ray absorption spectroscopy and medium energy ion scattering measurements have confirmed that the interfacial nitrogen is indeed removed. However, there are reactions between the Ge substrate and deposited high-K dielectrics, as deposited and after annealing to 600–800°C, Ge–O bonding into the high-K gate stacks which result in increased levels of conduction band edge defect states that incorporate these Ge atoms.

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Section: B Meis: Elimination Of Interfacial Ge-n Bonding During Postmentioning

confidence: 66%

Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Predeposition plasma nitridation process applied to Ge substrates to passivate interfaces between crystalline-Ge substrates and Hf-based high-K dielectrics

Lucovsky

Long

Chung

et al. 2009

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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“…Lucovsky et al found band offsets of 1.35-1.55 eV using ultraviolet photoemission spectroscopy measurements. 9 Values of 0.9-1.5 eV and 1.04 eV have been reported by Kobayashi et al 12 and Ohta et al, 13 respectively, from x-ray photoemission spectroscopy measurements. Afanas'v et al have reported the band offset of 1.44-1.84 eV from internal photoemission measurements; however, the GeO 2 band gap they found is around 4.3 eV, more than 1 eV lower than 5.5-5.7 eV reported by the others.…”

Section: Introductionmentioning

confidence: 80%

Bound states within the notch of the HfO2/GeO2/Ge stack

Wang

Ralph

Sedghi

et al. 2013

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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A model is presented to allow calculation of the bound states in the conduction band notch at the interface between the interfacial native GeO2 and high-κ dielectric layer in a Ge MOSFET gate stack. The notch represents a potential charge trapping site, which can induce threshold voltage instability. The model is applied to a three-dimensional structure, and the number of electrons or average occupancy of confined electrons in the notch is calculated. The effect of device physical and electrical parameters on the number of bound states and average occupancy of states in the notch is discussed. The significance of the confined charge in the notch and its effect on the threshold voltage shift in an 8-nm node Ge MOSFET is investigated. The main conclusion is that charge storage in this notch is insignificant at the relevant technology node.

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“…In addition, as shown in Fig. 1, compared to Si 3 N 4 , Ge 3 N 4 has a larger valence/conduction band offset with respect to SiO 2 tunnel oxide [14], [15], which makes Ge 3 N 4 a promising candidate 1536-125X/$31.00 © 2013 IEEE to achieve higher operation speed [16]- [18] and superior retention [19]. Although Ge-incorporated HfON has been proposed to enhance the charge-trapping capability for nonvolatile memory [20], most Ge-related materials for charge-trapping applications are pertinent to nanocrystal-based trapping media.…”

Section: Introductionmentioning

confidence: 97%

Electrical Characteristics for Flash Memory With Germanium Nitride as the Charge-Trapping Layer

Lin

et al. 2013

IEEE Trans. Nanotechnology

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Due to a larger band offset and a higher permittivity compared to Si 3 N 4 , Ge 3 N 4 formed by NH 3 plasma nitridation of an amorphous Ge film was explored in this study as the chargetrapping layer for flash memory devices. As the nitridation time prolongs, memory window and operation speed are improved accordingly. The improvement is inferred to be the increased number of trapping sites and higher permittivity of the charge-trapping layer caused by the introduction of nitrogen atoms. The former is helpful in storing more charges while the latter offers a higher electric field over the tunnel oxide. Memory devices with 180-s NH 3 plasma nitridation hold great potential for advanced memory applications because they possess many promising characteristics such as a large hysteresis memory window, high operation speed, robust endurance performance up to 10 5 program/erase (P/E) cycles, and good retention characteristic with 15% charge loss after 10-year operation at 85 • C.

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Elimination of GeO2 and Ge3N4 interfacial transition regions and defects at n-type Ge interfaces: A pathway for formation of n-MOS devices on Ge substrates

Cited by 26 publications

References 16 publications

Predeposition plasma nitridation process applied to Ge substrates to passivate interfaces between crystalline-Ge substrates and Hf-based high-K dielectrics

Predeposition plasma nitridation process applied to Ge substrates to passivate interfaces between crystalline-Ge substrates and Hf-based high-K dielectrics

Bound states within the notch of the HfO2/GeO2/Ge stack

Electrical Characteristics for Flash Memory With Germanium Nitride as the Charge-Trapping Layer

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