Eliminating microarchitectural dependency from Architectural Vulnerability

Sridharan, Vilas; Kaeli, David

doi:10.1109/hpca.2009.4798243

Cited by 137 publications

(79 citation statements)

References 21 publications

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“…This analysis was rebutted, and the effects pointed out by Wang were incorporated into an ACE analysis infrastructure [8]. Sridharan and Kaeli extended the notion of vulnerability to allow independent measurement of the vulnerability of programs and hardware [32] [33]. There have also been several publications that estimate AVF using architectural or microarchitectural state [26] [40] and that measure the AVF of GPUs [13] [38].…”

Section: Existing Multi-bit Remediation Techniquesmentioning

confidence: 99%

Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults

Wilkening

Sridharan

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Reliability is an important design constraint in modern microprocessors, and one of the fundamental reliability challenges is combating the effects of transient faults. This requires extensive analysis, including significant fault modeling to allow architects to make informed reliability tradeoffs. Recent data shows that multi-bit transient faults are becoming more common, increasing from 0.5% of SRAM faults in 180nm to 3.9% in 22nm, and are predicted to be even more prevalent in smaller technology nodes. Therefore, accurately modeling the effects of multi-bit transient faults is increasingly important to the microprocessor design process.Architecture vulnerability factor (AVF) analysis is a method to model the effects of single-bit transient faults. In this paper, we propose a method to calculate AVFs for spatial multi-bit transient faults (MB-AVFs) and provide insights that can help reduce the impact of these faults. First, we describe a novel multi-bit AVF analysis approach for detected, uncorrected errors (DUEs) and show how to measure DUE MB-AVFs in a performance simulator. We then extend our approach to measure SDC MB-AVFs. We find that MB-AVFs are not derivable from single-bit AVFs. We also find that larger fault modes have higher MB-AVFs. Finally, we present a case study on using MB-AVF analysis to optimize processor design, yielding SDC reductions of 86% in a GPU vector register file.

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Section: Existing Multi-bit Remediation Techniquesmentioning

confidence: 99%

Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults

Wilkening

Sridharan

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

Self Cite

View full text Add to dashboard Cite

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“…In contrast, our work is from the applications' perspective, and focuses on understanding the behavior of GPGPU applications under errors. Program Vulnerability Factor (PVF) is a metric proposed by Sridharan et al [23] to apply AVF analysis at the application layer. While this takes application properties into account, it still does not consider the end-to-end impact of faults on the application.…”

Section: Related Workmentioning

confidence: 99%

GPU-Qin: A methodology for evaluating the error resilience of GPGPU applications

Fang

Pattabiraman

Ripeanu

et al. 2014

2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

122

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Abstract-While graphics processing units (GPUs) have gained wide adoption as accelerators for general-purpose applications (GPGPU), the end-to-end reliability implications of their use have not been quantified. Fault injection is a widely used method for evaluating the reliability of applications. However, building a fault injector for GPGPU applications is challenging due to their massive parallelism, which makes it difficult to achieve representativeness while being time-efficient. This paper makes three key contributions. First, it presents the design of a fault-injection methodology to evaluate end-to-end reliability properties of application kernels running on GPUs. Second, it introduces a fault-injection tool that uses real GPU hardware and offers a good balance between the representativeness and the efficiency of the fault injection experiments. Third, this paper characterizes the error resilience characteristics of twelve GPGPU applications.

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“…As AVF represents the combined effect of the workload and its interaction with the hardware, Sridharan and Kaeli [20] attempt to decouple the software component of AVF from the hardware component through a microarchitecture-independent metric called Program Vulnerability Factor (PVF). PVF has been shown to model the AVF of the Architected Register File using inexpensive profiling.…”

Section: Related Workmentioning

confidence: 99%

A first-order mechanistic model for architectural vulnerability factor

Nair¹,

Eyerman²,

Eeckhout³

et al. 2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

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Soft error reliability has become a first-order design criterion for modern microprocessors. Architectural Vulnerability Factor (AVF) modeling is often used to capture the probability that a radiation-induced fault in a hardware structure will manifest as an error at the program output. AVF estimation requires detailed microarchitectural simulations which are time-consuming and typically present aggregate metrics. Moreover, it requires a large number of simulations to derive insight into the impact of microarchitectural events on AVF. In this work we present a first-order mechanistic analytical model for computing AVF by estimating the occupancy of correct-path state in important microarchitecture structures through inexpensive profiling. We show that the model estimates the AVF for the reorder buffer, issue queue, load and store queue, and functional units in a 4-wide issue machine with a mean absolute error of less than 0.07. The model is constructed from the first principles of out-of-order processor execution in order to provide novel insight into the interaction of the workload with the microarchitecture to determine AVF. We demonstrate that the model can be used to perform design space explorations to understand trade-offs between soft error rate and performance, to study the impact of scaling of microarchitectural structures on AVF and performance, and to characterize workloads for AVF.

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Eliminating microarchitectural dependency from Architectural Vulnerability

Cited by 137 publications

References 21 publications

Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults

Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults

GPU-Qin: A methodology for evaluating the error resilience of GPGPU applications

A first-order mechanistic model for architectural vulnerability factor

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