Electrothermal Monte Carlo Simulation of Submicrometer Si/SiGe MODFETs

Abstract-We apply a unique three-dimensional (3D) physics-based atomistic simulator to study silicon-rich (SiOx, x<2) resistive switching nonvolatile memory (RRAM) devices. We couple self-consistently a simulation of ion and electron transport to the 'atomistic' simulator GARAND and a selfheating model to explore the switching processes in these structures. The simulation model is more advanced than other available phenomenological models based on the resistor breaker network. The simulator is calibrated with experimental data, and reconstructs accurately the formation and rupture of the conductive filament in the 3D space. We demonstrate how the simulator is useful for exploring the little-known physics of these promising devices, and show that switching is an intrinsic property of the SiOx layer. In general, the simulation framework is useful for providing efficient designs, in terms of performance, variability and reliability, for memory devices and circuits. The simulator validity is not limited to SiOx-based devices, and can be used to study other promising RRAM systems based, e.g., on transition metal oxides.

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“…using a more advanced in-house solver, as compared to timeindependent HDE solvers employed for example in [18]- [20].…”

Section: The Simulation Modelmentioning

confidence: 99%

Self-consistent physical modeling of SiOx-based RRAM structures

Sadi

Wang

Gerrer

et al. 2015

2015 International Workshop on Computational Electronics (IWCE)

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“…In all our investigations we have pursued this approach for the description of the phonon bath. A variant of this approach, that has been pursued by the Leeds group [27] and by Eric Pop and co-workers [21], counts the number of generated acoustic and optical phonons in a given branch and mode. Then, the total heat generation rate per unit volume is computed as…”

Section: Some General Considerations About the Solution Of The Heat Tmentioning

confidence: 99%

Modeling heating effects in nanoscale devices: the present and the future

Vasileska

Raleva²,

Goodnick

2008

J Comput Electron

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In this review paper we give an overview on the present state of the art in modeling heat transport in nanoscale devices and what issues we need to address for better and more successful modeling of future devices. We begin with a brief overview of the heat transport in materials and explain why the simple Fourier law fails in nanoscale devices. Then we elaborate on attempts to model heat transport in nanostructures from both perspectives: nanomaterials (the work of Narumanchi and co-workers) and nanodevices (the work of Majumdar, Pop, Goodson and recently Vasileska, Raleva and Goodnick). We use our own simulation results which we have used to examine heat transport in nanoscaling devices to point out some important issues such as the fact that thermal degradation does not increase as we decrease feature size due to the more pronounced non-stationary transport and ballistic transport effects in nanoscale devices. We also point out that instead of using SOI, if one uses Silicon on Diamond technology there is much less heat degradation and better spread of the heat in the Diamond material. We also point out that tools for thermal modeling of nanoscale devices need to be improved from the present state of the art as 3D tools are needed, for example, to simulate heat transport and electrical transport in a FinFET device. Better models than the energy balance equations for the acoustic and optical phonons what we presently use in our simulators are also welcomed. The ultimate goal is to design the tool that can be efficient enough but at the same time can simulate most accu-D. Vasileska ( ) · S.M. Goodnick rately both electrons and phonons within the particle pictures by solving their corresponding Boltzmann transport equations self-consistently. Investigations in integration of Peltier coolers with CMOS technology are also welcomed and much needed to reduce the problem of heat dissipation in nanoscale devices and interconnects.

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“…As a result, there is a growing demand for the development of reliable electrothermal models and tools treating more accurately the self-heating effects in nano CMOS devices [1][2][3]. Simultaneously FinFETs, with their superior electrostatic integrity, performance and variability are replacing the traditional planar MOSFET [4].…”

Section: Introductionmentioning

confidence: 99%

Simulation analysis of the electro-thermal performance of SOI FinFETs

Wang

Sadi

Brown

et al. 2016

2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

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Abstract-The GSS 'atomistic' simulator GARAND has been enhanced with a thermal simulation module to investigate the impact of self-heating on FinFET DC operation. This thermal simulation module is based on the solution of the coupled Heat Flow, Poisson, and Current Continuity Equations, which is developed for the benefit of computational efficiency. A new formula for the calculation of the thermal conductivity in the fin region is employed considering both fin shape and temperature dependencies. The heat dissipation through the gate is treated by nonhomogeneous Neumann boundary conditions. The electrothermal simulation results for an SOI FinFET example, designed to meet the specifications for the 14/16nm CMOS technology generation, are presented. The lattice temperature profiles under different external thermal resistances connected to the gate and the corresponding Id-Vg characteristics are investigated and analysed.

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Electrothermal Monte Carlo Simulation of Submicrometer Si/SiGe MODFETs

Cited by 30 publications

References 23 publications

Self-consistent physical modeling of SiOx-based RRAM structures

Self-consistent physical modeling of SiOx-based RRAM structures

Modeling heating effects in nanoscale devices: the present and the future

Simulation analysis of the electro-thermal performance of SOI FinFETs

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