Modeling heating effects in nanoscale devices: the present and the future

Abstract

In this review paper we give an overview on the present state of the art in modeling heat transport in nanoscale devices and what issues we need to address for better and more successful modeling of future devices. We begin with a brief overview of the heat transport in materials and explain why the simple Fourier law fails in nanoscale devices. Then we elaborate on attempts to model heat transport in nanostructures from both perspectives: nanomaterials (the work of Narumanchi and co-workers) and nanodevices (the work of Majumdar, Pop, Goodson and recently Vasileska, Raleva and Goodnick). We use our own simulation results which we have used to examine heat transport in nanoscaling devices to point out some important issues such as the fact that thermal degradation does not increase as we decrease feature size due to the more pronounced non-stationary transport and ballistic transport effects in nanoscale devices. We also point out that instead of using SOI, if one uses Silicon on Diamond technology there is much less heat degradation and better spread of the heat in the Diamond material. We also point out that tools for thermal modeling of nanoscale devices need to be improved from the present state of the art as 3D tools are needed, for example, to simulate heat transport and electrical transport in a FinFET device. Better models than the energy balance equations for the acoustic and optical phonons what we presently use in our simulators are also welcomed. The ultimate goal is to design the tool that can be efficient enough but at the same time can simulate most accu-D. Vasileska ( ) · S.M. Goodnick rately both electrons and phonons within the particle pictures by solving their corresponding Boltzmann transport equations self-consistently. Investigations in integration of Peltier coolers with CMOS technology are also welcomed and much needed to reduce the problem of heat dissipation in nanoscale devices and interconnects.

Energy dissipation and transport in nanoscale devices

“…This was the approach adopted in Refs. [58,[61][62][63][64], where power dissipation was computed as a sum of all phonon emission minus all phonon absorption events: where n is the real-space carrier density, N sim is the number of simulated particles (e.g. 10,000 simulated particles could be used to describe 10 19 cm -3 real-space concentration) and Δt is the time.…”

Lattice thermal conductivity of graphene nanostructures

“…Advances in nanotechnology demand a better understanding of heat transport in nanoscale systems. The increased levels of dissipated power in ever smaller devices make the search for high thermal conductors essential [1][2][3].…”

Enhancing phonon flow through one-dimensional interfaces by impedance matching

“…At length scales on the order of tens of nanometers, phonons flow quasi-ballistically and scattering at interfaces plays a dominant role on the overall thermal conductance [1][2][3][4][5]. Many applications stand to benefit from decreasing interfacial scattering; for instance, the heat generated in current transistors is blocked by their low thermal conductance [6,7], raising device temperature and impacting performance and reliability [8]. One way to increase interfacial conductance is by inserting a thin junction layer that allows a gradual change of material properties and bridges phonons across the junction.…”