Electronic-photonic integrated circuits on the CMOS platform

Kimerling, Lionel C.; Ahn, Donghwan; Apsel, Alyssa; Beals, Mark; Carothers, Daniel; Chen, Y.-K.; Conway, T. J.; Gill, Douglas M.; Grove, Michael; Hong, Ching-yin; Lipson, Michal; Liu, Jifeng; Michel, Jürgen; Pan, Dong; Patel, Sanjay; Pomerene, Andrew; Rasras, Mahmoud; Sparacin, Daniel K.; Tu, Kun-Yii; White, Alice E.; Wong, Chee Wei

doi:10.1117/12.654455

Cited by 120 publications

(37 citation statements)

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“…The application of a high contrast materials system (Δn≈0.55) for the highly selective MR-based filters allows for the creation of complex devices on a small footprint [9][10][11][12][13]. It should noted, however, that the devices reported here could also be realized readily in silicon waveguides using the vertically stacked double silicon-on-insulator photonic system that was reported recently [14]. For such a silicon photonic system, the device architectures would be exactly the same as we have presented here.…”

Section: Design and Fabricationmentioning

confidence: 96%

Densely integrated microring resonator based photonic devices for use in access networks

Klein¹,

Urban²,

Sengo³

et al. 2007

Opt. Express

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Section: Design and Fabricationmentioning

confidence: 96%

Densely integrated microring resonator based photonic devices for use in access networks

Klein¹,

Urban²,

Sengo³

et al. 2007

Opt. Express

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“…The detailed steps required for CMOS electronics are assumed in the flow and omitted for here simplification. [7,8,9] A schematic view of the FEOL process sequence to fabricate photonic devices is shown in Figure 3. The major steps include: i) optical waveguide fabrication for routers, filters and couplers; ii) electrode formation, growth and planarization of germanium and iii) contact and interconnect metallization.…”

Section: Ulsi Monolithic Microphotonic Integrationmentioning

confidence: 99%

Monolithic Microphotonic Integration on the Silicon Platform

Kimerling

Michel

2011

ECS Trans.

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Photonic integration in ULSI electronic circuits contributes three new functionalities that are critical to performance scaling: i) power efficient, global interconnection, ii) high bandwidth density chip-chip communication, and iii) optical signal processing. With the transition to parallel chip architectures, efficient communication among processing nodes can become a limiting factor to both programming and performance. A photonic communication layer can provide distance independent, low latency interconnection with efficient broadcast capability. On-chip photonic signal channels can provide wavelength division multiplexed, photonic pins with >100x improvement in I/O bandwidth density over ball grid arrays. Monolithic integration of these capabilities in the CMOS process flow can be achieved with Ge active devices (photodetectors, modulators, lasers) and Si/SiON passive components (waveguides, resonators, couplers). Process integration can be achieved with both FEOL and BEOL strategies. Scaling Information Technology: Energy, Bandwidth, and CostInformation Technology (IT), enabled by ULSI silicon, has produced exponential increases in communication capacity (bits/second) and computation performance (operations-per-second) at constant cost. Internet traffic is increasing today at a pace of 40%/year and computation performance follows a Moore's Law pace of 100x/decade at the chip level and a faster 1000x/decade at the system level (facilitated by increased parallelism in system architecture). These paced advances, heralded as The Information Age, have been enabled by an integrated CMOS hardware platform that has delivered required improvements in power efficiency, performance and cost by dimensional scaling. Today the challenges of energy consumption and communication bandwidth call for a new scaling paradigm based on the integration of photonic functionality in CMOS. This paper is written as a guide to the technology and implementation strategies for photonic integration with ULSI electronics. It bridges CMOS and fiber optic technologies to attract a community to this new chip platform. [1,2,3] While the demand for increasing IT performance seems secure, the path for delivering that performance has encountered several significant barriers. The projected energy consumption by Information Technology has become an unsustainable fraction of the world electrical power generation. Server farms require >100MW of power; the IP switching to route Internet messages consumes ~10TWhr/year/telecom-carrier; servers, IP-traffic and peripherals use, in aggregate, ~5% of national electricity generation with predictions of >100% by 2020.The bandwidth barrier to scaling is evident in the information processing guideline (Amdahl's Law) of one Byte of communication for

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“…As shown in Figure 1.5, this is a miniaturized RF-channelizer optical receiver actuated by an off-chip laser [22][23]. An incoming broadband RF signal modulates the lightbeam on-chip, and the optical filter banks pick off spectral 'slices' of the RF waveform.…”

Section: The Present Status Of Oeicsmentioning

confidence: 99%

Introduction: The Opto‐Electronic Integrated Circuit

Soref

2008

Silicon Photonics

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Electronic-photonic integrated circuits on the CMOS platform

Cited by 120 publications

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Densely integrated microring resonator based photonic devices for use in access networks

Densely integrated microring resonator based photonic devices for use in access networks

Monolithic Microphotonic Integration on the Silicon Platform

Introduction: The Opto‐Electronic Integrated Circuit

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