Electromigration behavior of interconnects between chip and board for embedded wafer level ball grid array (eWLB)

Bauer, R. S.; Fischer, A.; Birzer, C.; Alexa, L.

doi:10.1109/ectc.2011.5898532

Cited by 5 publications

(13 citation statements)

References 6 publications

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“…Several representative resistance traces are shown in The authors further note that there is an appearance of bimodality in the resistance traces, which has also been observed on similar structures by R. Bauer, et al [5]. As such, the lifetime distributions in the next section are based on the first mode of failure, which is the more limiting failure mode for the calculation of current-carrying capability (Imax) of these process legs.…”

Section: Resistance Tracesmentioning

confidence: 72%

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Electromigration of solder balls for wafer-level packaging with different under bump metallurgy and redistribution layer thickness

Hau-Riege

Keser

Yau

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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Electromigratio n (EM) has b een cond ucted on lead -free solder balls in wafer-level packages for different redistribution layer (RDL) thicknesses, under bump metallurgy (UBM) schemes, and lead-free solder alloys. Two different types of EM-induced voids were observed at the electron-source side: pancake void between the solder/RDL interface and throughthickness voids in the RDL. In both cases, voids formed at the interface of CuSn intermetallic compound and solder. A Nilayer in the UBM was found to prolong EM lifetime by slowing the diffusion of Sn into the Cu RDL relative to a Cuonly UBM. The absence of UBM led to the shortest EM lifetime due to direct contact of solder to RDL. Also, a thicker RDL extended lifetime proportionately to the decrease in current density and Joule heating at the critical interface. On the other hand, adding Ni and Ge to the SAC alloy did not statistically impact lifetime. IntroductionWafer-level packaging (WLP) achieves a small-form factor and lower cost by eliminating the package substrate, and connecting the die directly to the printed circuit board (PCB) via solder balls.When materials, geometries, and/or structures change, the entire system needs to be re-characterized for board level reliability. These changes can include redistribution layer (RDL) material and thickness, underbump metallurgy (UBM) material and thickness, and solder ball metallurgy. This paper describes the impact of such changes on electromigration. Related papers investigate other aspects of board level reliability including drop shock and temperature cycle [1][2]. Fundamentally, EM is the self-diffusion of metal(s) induced by electric current, which can lead to voiding and interconnect failure, and is an area of major reliability concern for interconnects. Electromigration lifetime quickly degrades with increasing temperature and current density, as described by the well-known Black's Law established in 1969 [3]:

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Section: Resistance Tracesmentioning

confidence: 72%

“…These factors are also relevant to package-level interconnects. More recently, EM behavior of solder balls (including WLP) is being discussed [4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Electromigration of solder balls for wafer-level packaging with different under bump metallurgy and redistribution layer thickness

Hau-Riege

Keser

Yau

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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“…Moreover, due to previously reported trace consumption issues [7,8] related to electromigration stress, there is also interest in examining the effect that Cu-RDL thickness has on device lifetime. To this end, two different Cu RDL thickness values are considered: 9µm and 14µm.…”

Section: Wafer Level Process Types Em Structure and Test Board Attrmentioning

confidence: 99%

“…Recent publications by Bauer et al [7] and Hau-Riege et al [8] have shown a number of different failure modes for Cu based UBM or RDL structures, but current carrying capacity for these structures is not provided.…”

Section: Introductionmentioning

confidence: 98%

“…While EM behavior of flip chip bump interconnects has been published [1][2][3][4][5][6], only a few studies [7][8][9][10] have focused on WLCSP or similar interconnects. Recent publications by Bauer et al [7] and Hau-Riege et al [8] have shown a number of different failure modes for Cu based UBM or RDL structures, but current carrying capacity for these structures is not provided.…”

Section: Introductionmentioning

confidence: 99%

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Electromigration reliability and current carrying capacity of various WLCSP interconnect structures

Syed

Karthikeyan

Berry

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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Wafer Level Chip Scale Packages (WLCSPs) are increasingly being used in Power Management IC (PMIC) applications. Since these packages are typically of small size and low I/O count, the current per bump can be very high for these applications. Therefore, it is important to characterize the electromigration (EM) behavior of WLCSP interconnects to estimate their current carrying capacity.This paper provides an EM performance comparison of four (4) different WLCSP interconnects tested under the same condition. The configurations included:ii) Ti/Cu/8.6µm Cu UBM on 4µm Cu RDL, iii) Bump-on-trace with 9µm thick Cu RDL, and iv) Bump-on-trace with 14µm thick Cu RDL. A specially designed test vehicle with multiple EM test structures was used for this purpose. The packages were mounted on printed wiring boards (PWB) with either Cu/OSP or NiAu pad surface finish. These assemblies were then tested in a dedicated EM test system using 1.0Amp/161 o C as the test condition. More than 4000 hours of testing have been completed so far. Clear differences between these WLCSP interconnects were observed in terms of EM performance. Samples were also removed at different times throughout the test so that detailed SEM analyses could be performed to understand and quantify the failure mode and progression of EM damage for each configuration. The EM performance is found to be significantly better for structures with a 2.0µm Ni UBM layer and the bump-on-trace structure with 14µm thick RDL with no failures so far. However, units with either 8.6µm thick Cu UBM structure or 9µm thick RDL bump-ontrace structure have resulted in a number of failures and at least 2X lower reliability compared to the other two structures. Further, PWB surface finish has a significant effect on EM performance with Cu/OSP performing better than NiAu finish.

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The impact of different under bump metallurgies and redistribution layers on the electromigration of solder balls for wafer-level packaging

Hau-Riege

Keser

Alvarado

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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Electromigration behavior of interconnects between chip and board for embedded wafer level ball grid array (eWLB)

Cited by 5 publications

References 6 publications

Electromigration of solder balls for wafer-level packaging with different under bump metallurgy and redistribution layer thickness

Electromigration of solder balls for wafer-level packaging with different under bump metallurgy and redistribution layer thickness

Electromigration reliability and current carrying capacity of various WLCSP interconnect structures

The impact of different under bump metallurgies and redistribution layers on the electromigration of solder balls for wafer-level packaging

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