Electromechanical properties of amorphous indium–gallium–zinc-oxide transistors structured with an island configuration on plastic

Abstract

A comparative study of the electromechanical properties was carried out on a low-temperature-processed amorphous indium–gallium–zinc-oxide thin-film transistor, particularly with regard to the structural design of the device under the stress accumulation of an outward bending surface. Shown herein is the reliable electromechanical integrity of island-structured devices against the mechanical strain at bending radii of mm order. The onset of crack strain also closely corresponded to the electrical failure of the stressed device. These results revealed that the island configuration on the bending surface effectively suppresses the stress accumulation on sheets composed of inorganic stacked layers in a uniaxial direction.

Metal oxide semiconductor thin-film transistors for flexible electronics

“…Moreover, also other properties like adhesion or transparency need to be considered. These requirements resulted in the use of different metals: Al, 77,149,152,154,157,165,170,172,179,208 Au, 38,167 Cu, 147 Mo, 41,82,137,138,148,164,168 palladium (Pd), 145 and Ti, 90,93,144,169 whereas Mo and Ti seem to exhibit the lowest specific contact resistance R C . At the same time, a big variety of multi-layer contacts have been developed to combine the advantageous properties of different materials; recent examples are: Ti/ Au, 59,69,81,84,113,140,141,143,146,150,151,[181][182][183] Ni/Au, 79 Mo/ Al, 166,173 Cr/Au, 114 Mo/AlNd, 156 Cr/Au/Cr, 92 Mo/Al/Mo, 153 Ti/Au/Ti, …”

“…162 In alternative to flexible substrates manufactured independently from the TFTs, it is also possible to create the flexible substrate by covering a host substrate with a polymer using either evaporation, 80,81,141 spin, slot or blade coating techniques. 23,39,133,135,137,142,144,147,155,161,164,179 The advantages of these fabrication techniques based on a rigid support are a high compatibility with the standard fabrication processes on Si or glass wafers, a reduction of the expansion of the substrate during the manufacturing process, as well as the possibility to realize devices on very thin (%1 lm) substrates. After the TFT fabrication is completed, the flexible foils or thin deposited polymer layers carrying the devices can be separated from the rigid support using: (1) mechanical peeling, 38,142,155,158,161,164,166,168,179 (2) a low adhesion releasing layer, 133,144 (3) a supporting laser, 137 or (4) a sacrificial layer between the host carrier and the polymer.…”

“…23,39,133,135,137,142,144,147,155,161,164,179 The advantages of these fabrication techniques based on a rigid support are a high compatibility with the standard fabrication processes on Si or glass wafers, a reduction of the expansion of the substrate during the manufacturing process, as well as the possibility to realize devices on very thin (%1 lm) substrates. After the TFT fabrication is completed, the flexible foils or thin deposited polymer layers carrying the devices can be separated from the rigid support using: (1) mechanical peeling, 38,142,155,158,161,164,166,168,179 (2) a low adhesion releasing layer, 133,144 (3) a supporting laser, 137 or (4) a sacrificial layer between the host carrier and the polymer. 78,80,81,141,147 To this regard, a direct comparison of different releasing methods by Lin et al showed that mechanical peeling of the flexible substrate from the hosting carrier wafer can lead to deformation and cracking of the TFTs in case of high adhesion forces between the polymer and the carrier.…”

“…RF and RF-magnetron sputtering have been used to deposit IGZO, 23,[80][81][82]96,132,[134][135][136]139,145,147,152,155,156,202,208 IZO, 184 GZO, 188 and ZnO. 59,78,177,178,180 Furthermore, IGZO was also deposited by DC sputtering 133,137,153,160,168 and pulsed DC sputtering. 40 The advantages of sputtering are the large availability of sputter tools, the low temperature (typically room temperature) deposition, as well as the good adhesion and dense structure of the final layers.…”

“…Furthermore, by using a TG configuration with metallic gate contacts, it is also possible to self-align SiO 2 gate dielectric to Mo gate electrodes in an RIE process. 137 This approach has the additional advantage that the RIE plasma increases the conductivity of the active layer (IGZO) in the contact areas. 137 Similarly, TG IGZO devices with highly conductive IGZO source/drain electrodes self-aligned to Mo gate contacts can be realized by PECVD-growing a SiN x after the TG patterning.…”