Electromagnetic coupling effects in RFCMOS circuits

Adan, A.O.; Fukumi, Minoru; Higashi, K.; Suyama, Takuya; Miyamoto, M.; Hayashi, Makoto

doi:10.1109/mwsym.2002.1011553

Cited by 20 publications

(14 citation statements)

References 4 publications

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“…Inductors in the chip are custom designed with the thickest top metal layer in the process to utilize its lower resistivity and capacitance to ground. There are two types of coupling mechanism: substrate coupling and electromagnetic coupling [21,22]. Additionally, the design of the matching inductors, L1, L2 and Insertion Loss (dB) Figure 11.…”

Section: Measurementmentioning

confidence: 99%

“…Particularly, placement of the inductors needs extra care since coupling between inductors deteriorates the Q's of adjacent inductors. There are two types of coupling mechanism: substrate coupling and electromagnetic coupling [21,22]. In order to alleviate substrate coupling between inductors, the perimeter of each inductor is covered by p + substrate contacts which are 50 mm away from the inductors.…”

Section: Return Loss (Db)mentioning

confidence: 99%

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A fully integrated, highly linear CMOS T/R switch for X‐Band phased array radars

Dinç¹,

Zihir²,

Gürbüz³

2012

Circuit Theory & Apps

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This paper presents the design and implementation of a single-pole, double-throw transmit/receive (T/R) switch for X-Band (8-12 GHz) phased array radar applications. The T/R switch was fabricated in a 0.25-mm SiGe BiCMOS process and occupies 0.44-mm 2 chip area, including pads. The design focuses on the techniques, primarily, to achieve higher power handling capability (P 1dB ), along with higher isolation and better insertion loss (IL) of the T/R switch. These techniques include resistive-body floating, using on-chip impedance transformation networks and DC biasing of all terminals of the T/R switch. In addition, optimization of transistor widths and parallel resonance technique are used to improve IL and isolation, respectively. All these design techniques resulted in a measured IL of 3.6 dB, isolation of 34.8 dB and IP 1dB of 28.2 dBm at 10 GHz. The return losses at both input and output ports are better than 16 dB from 8 to 12 GHz. To our knowledge, this paper presents the single-ended CMOS T/R switch with the highest IP 1dB , competitive isolation and comparable IL at X-Band, compared to other reported works in the literature and attributed to the unique design methodologies and techniques.

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Section: Measurementmentioning

confidence: 99%

Section: Return Loss (Db)mentioning

confidence: 99%

A fully integrated, highly linear CMOS T/R switch for X‐Band phased array radars

Dinç¹,

Zihir²,

Gürbüz³

2012

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…A new substrate network consisting L sub , R sub , M sub , and C sub is introduced to account for substrate loss. It is reported [16][17] that a parallel combination of resistance and capacitance should be included in the modeling of two metal strips on a silicon substrate. Since the current flowing through the low resistive substrate is large enough, we introduce inductance to represent substrate eddy current effect through lateral substrate coupling.…”

Section: B Proposed New Compact Inductor Model With Substrate Networkmentioning

confidence: 99%

Broadband scalable model for Si-RF on-chip spiral inductors with substrate eddy current effect

Mandal

Sural

Patra

2007

Int J RF and Microwave Comp Aid Eng

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A new broadband scalable compact model for on-chip spiral inductor is presented. It includes a substrate network and a high resistive component to accurately capture the substrate eddy current effect, skin and proximity effects at high frequencies. The proposed model shows a good match with the measurement results over a frequency range of up to 20 GHz. An automated parameter extraction and optimization procedure has been developed using equivalent circuit analysis and particle swarm optimization. We achieved good scalability for all model parameters with respect to spiral layout geometry.

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“…Hence design techniques include Q factor optimization at operating frequencies. However maximization of Q has a negative influence on coupling resulting in a trade-off with the reverse isolation (S 12 ) of the LNA [6]. The influence of such high Q designs will be presented in the final section.…”

Section: On-chip Spiral Inductors In Cmos Cascode Lnasmentioning

confidence: 99%

“…Following this, the coupling effects between the load inductors of a two stage common source CMOS LNA around 1 GHz are also studied. In [6]- [8] several attempts were made to model both inter-device EM coupling and substrate coupling effects through lumped elements around 6 GHz in CMOS implementations.…”

Section: Introductionmentioning

confidence: 99%

On-chip Electromagnetic Interactions in CMOS Cascode LNAs

Subramanian¹,

Boeck²

2007

2007 IEEE International Workshop on Radio-Frequency Integration Technology

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Target of this work is to explain the significance of electromagnetic effects due to on-chip spiral inductors and passive interconnects on the circuit behavior. Starting from the design aspects of spiral inductors in a cascode CMOS LNA, the influence of their on-chip coupling on the reverse isolation performance of the amplifier will be presented. The importance of the careful consideration of on-chip spiral inductor shielding and substrate coupling effects are detailed and justified by comparison with the measured S-parameter results. Finally, it will be shown that by considering all the on-chip spirals and critical passives through electromagnetic analysis it is possible to estimate very precisely the measured isolation, gain and matching characteristics of a cascode CMOS low noise amplifier around 6 GHz frequency of operation.

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Electromagnetic coupling effects in RFCMOS circuits

Cited by 20 publications

References 4 publications

A fully integrated, highly linear CMOS T/R switch for X‐Band phased array radars

A fully integrated, highly linear CMOS T/R switch for X‐Band phased array radars

Broadband scalable model for Si-RF on-chip spiral inductors with substrate eddy current effect

On-chip Electromagnetic Interactions in CMOS Cascode LNAs

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