On-chip Electromagnetic Interactions in CMOS Cascode LNAs

Subramanian, Viswanathan; Boeck, Georg

doi:10.1109/rfit.2007.4443959

Cited by 3 publications

(1 citation statement)

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“…In order to 978-1-4244-5357-3/09/$26.00©20091 EEE mitigate this problem , all the realized on-chip spiral inductors use patterned ground shielding based on the bottom metal layer (metal 1) [2]. High Q inductive transmission lines with trench-isolation (TI) shielding have also been incorporated in the design.…”

Section: A Amplifier Topologymentioning

confidence: 99%

Fully integrated high efficiency K-band PA in 0.18 µm CMOS technology

Portela

Subramanian

Boeck

2009

2009 SBMO/IEEE MTT-S International Microwave and Optoelectronics Conference (IMOC)

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A fully integrated 2 stage K-band power amplifier is designed, fabricated and measured. The amplifier is realized utilizing standard 0.18/lm CMOS process. A novel simplified matching and bias network is used in order to reduce the input and output losses and to achieve a high output power and PAE. At 24 GHz, the measured results of the amplifier are, a smallsignal power gain of 16.2 dB, a maximum output power of 17.5 dBm, 13.6 dBm of output power at 1 dB compression point and a peak PAE of22.5 %. To the best of the author's knowledge, this is the highest PAE ever reported for a CMOS power amplifier in this frequency range using 0.18 urn CMOS technology. RF I~'-" II Vo I. INTRODUC TIONT HE ever increasing demand for a high-date-rate short range communication is strongly pushing the CMOS development at higher frequencies. The availability of license free Industrial, Scientific and Medical Band (ISM) at 24 GHz has significantly contributed to the amount of research being done at this frequency.In this work, a PA with simplified lumped element matching networks is presented. The PAis designed utilizing a standard 0.18 urn CMOS technology. It is a 7 metal layer process with two thick metal levels on the top for on-chip transmission line and spiral inductor realization. In the design, microstrip transmission lines based on the top metal of 4 urn thickness have been extensively used for matching as well as for biasing. Fig. 1 shows a simplified schematic of the power amplifier. As it can be seen in Fig. 1, a casco de structure is adopted for both stages. Compared to a single MOS transistor, the cascode structure provides a higher gain and makes the device more unilateral [1]. The voltage used to bias this structure is divided between the two transistors on the stack. This allows a higher voltage to be used without suffering from hot carrier degeneration. Since the cascode structure makes the device more unilateral, it also facilitates the design stability. PA DESIGN PROCEDURES A. Amplifier TopologyThe substrate effect resulting from the magnetic coupling between the on-chip spiral and the semi-conducting silicon significantly reduces the inductor quality factor. In order to 978-1-4244-5357-3/09/$26.00©20091 EEE Fig. I. Simplified schematic ofthe power amplifier. mitigate this problem , all the realized on-chip spiral inductors use patterned ground shielding based on the bottom metal layer (metal 1) [2]. High Q inductive transmission lines with trench-isolation (TI) shielding have also been incorporated in the design.In order to reduce the loss and increase the efficiency, a simplified matching network based on lumped components is used. In this matching network, the components needed to bias the transistor are also used to perform the input, output and inter-stage matching. This can significantly reduce the number of components needed, and since lumped components are a major source of loss, reducing the number of components also reduce the total power loss, and facilitates the achievement of a high output power, gain an...

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Section: A Amplifier Topologymentioning

confidence: 99%