Electrical simulation and measurement of IPD with multilayer thin film technology for WLP

Siew, Glen; Soh, Serine; Tee, Tong Yan; Chen, Haoyang; Kang, In Soo; Kim, Jong Heon

doi:10.1109/icept.2011.6066918

2011 12th International Conference on Electronic Packaging Technology and High Density Packaging 2011

DOI: 10.1109/icept.2011.6066918

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Electrical simulation and measurement of IPD with multilayer thin film technology for WLP

Glen Siew¹,

Serine Soh²,

Tong Yan Tee³

et al.

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Cited by 9 publications

References 4 publications

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Wafer level packaging of MEMS and 3D integration with CMOS for fabrication of timing microsystems

Manier

Zoschke

Wilke

et al. 2016

2016 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP)

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The following paper gives an insight on the packaging concepts and fabrication processes used to ultimately manufacture a timing module at wafer scale. The packaging of the timing module consists in the integration of an ASIC together with a Quartz-based or Twin-Silicon resonator MEMS which require to be hermetically sealed under vacuum for proper function. The 3D-integration enables a significant miniaturization of the complete system. Subsequently a BAW (Bulk Acoustic Wave) resonator can be further associated over the quartz resonator to form a MEMS-based freely programmable oscillator for stable clock generation, covering a large frequency range between 1 and 50 MHz. The principal fabrication processes include the implementation of Through-Silicon Vias (TSV) in active CMOS wafers, temporary wafer bonding for thin wafer handling and wafer bonding for metallic sealing under vacuum and formation of electrical interconnects. The components were packaged by chip to wafer assembly onto active CMOS wafers with TSVs and subsequent wafer to wafer bonding with a corresponding cavity cap wafer for vacuum encapsulation. All processes have been developed and performed at 200 mm industrial wafer scale

show abstract

Wafer level packaging of MEMS and 3D integration with CMOS for fabrication of timing microsystems

Manier

Zoschke

Wilke

et al. 2016

2016 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP)

View full text Add to dashboard Cite

show abstract

Prototyping of low-cost wafer level packages

Chen¹,

Tee²,

Siew³

et al. 2011

2011 IEEE 13th Electronics Packaging Technology Conference

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Development of low-cost wafer level package through integrated design and simulation analysis

Tee¹,

Siew²,

Chen³

et al. 2011

2011 12th International Conference on Electronic Packaging Technology and High Density Packaging

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Electrical simulation and measurement of IPD with multilayer thin film technology for WLP

Cited by 9 publications

References 4 publications

Wafer level packaging of MEMS and 3D integration with CMOS for fabrication of timing microsystems

Wafer level packaging of MEMS and 3D integration with CMOS for fabrication of timing microsystems

Prototyping of low-cost wafer level packages

Development of low-cost wafer level package through integrated design and simulation analysis

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