Electrical Properties of Ultrathin Hf-Ti-O Higher k Gate Dielectric Films and Their Application in ETSOI MOSFET

Abstract

Ultrathin Hf-Ti-O higher k gate dielectric films (~2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) ~9.4%, low equivalent gate oxide thickness (EOT) of ~0.69 nm and acceptable gate leakage current density of 0.61 A/cm2 @ (V fb − 1)V could be obtained. The conduction mechanism through the gate dielectric is dominated by the F-N tunneling in the gate voltage range of −0.5 to −2 V. Under the same physical thickness and process flow, lower EOT and higher I on/I off ratio could be obtained while using Hf-Ti-O as gate dielectric compared with HfO2. With Hf-Ti-O as gate dielectric, two ETSOI PMOSFETs with gate width/gate length (W/L) of 0.5 μm/25 nm and 3 μm/40 nm show good performances such as high I on, I on/I off ratio in the magnitude of 105, and peak transconductance, as well as suitable threshold voltage (−0.3~−0.2 V). Particularly, ETSOI PMOSFETs show superior short-channel control capacity with DIBL <82 mV/V and subthreshold swing <70 mV/decade.

Integration of Highly Strained SiGe in Source and Drain with HK and MG for 22 nm Bulk PMOS Transistors

“…where ν is Poisson ratio for SiGe ( ν = 0.287) and β is the contraction coefficient of boron in Si (6.3 ± 0.1 × 10 −24 cm 3 /atom) [ 14 ]. The extracted value shows a boron doping level of 1–3 × 10 20 cm −3 .…”

“…This article mainly presents how to grow highly strained SiGe film for source and drain application for 22 nm pMOSFETs with high-k and metal gate. The high-k material is HfO 2 thin film and filling metal in the trench was B-doped W layer, both of these films are deposited by ALD technology [ 13 , 14 ]. This study provides the knowledge of how to grow and apply high-quality selective epitaxy SiGe film in the transistor structures for advanced technology nodes.…”

Analytical Modeling and Simulation of Nanoscale Fully Depleted Dual Metal Gate SOI MOSFET

“…SOI devices were made to effectively suppress the SCEs but still, SOI devices are not able to completely free from SCE [15]. The short channel effects mainly found in SOI devices are kink effect (at high drain voltage, for transistor operating above threshold), self heating mechanism as the buried oxide makes a good thermal isolation to Silicon substrate, drain current overshoot, latch effect which is observed when SOI MOSFET operates at subthreshold region and complexity in formation of thin Silicon films [18][19][20].…”

“…However, still, there are some SCE which arise when SOI is in nano regimes. To improve the SOI characteristics for very narrow channel device, many improved SOI structure is suggested by researchers [3,[13][14][15]. The Dual Material Gate (DMG) is one of such structure having a metal gate made with two dissimilar metals having different work-function.…”