Electrical performances degradations and physics based mechanisms under negative bias temperature instability stress for p-GaN gate high electron mobility transistors

Zhang, Chi; Liu, Siyang; Li, Sheng; Tao, Xinyi; Hou, Bo; Zhou, Bin; Wei, Jiaxing; Chen, Yiqiang; Sun, Weifeng

doi:10.1088/1361-6641/abc1b3

Cited by 12 publications

(8 citation statements)

References 21 publications

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“…In contrast, the negative Δ V T results from hole accumulation. The behavior of Δ V T could be linked to three physical processes, as illustrated in Figure 8 a,b: Donor-type hole trap states at the p-GaN/AlGaN interface could be activated and release holes to the valence band in the p-GaN layer [ 17 , 18 ]; The depletion width of SCR, in the p-GaN layer of SG HEMTs, would decrease under the negative gate bias stress, which also leads to hole release [ 4 ]; Holes could flow from the gate-source drift region, towards the gate stack, and under large negative gate bias stress. Part of the holes may flow out to the gate terminal and contribute to the gate current, while part of the holes may get trapped into the gate stack region and lead to an extra hole accumulation [ 16 ].…”

Section: Resultsmentioning

confidence: 99%

“…The gate bias stress-induced threshold voltage ( V T ) instability of p-GaN gate HEMTs has been widely investigated recently, and the imbalanced extra charge accumulation, caused by the (de-) trapping of holes or electrons in the gate stack region, has been proposed as the main physical cause [ 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 ]. Considering that normally-off p-GaN gate devices feature a relatively low V T voltage, applying negative gate voltage is an important method for improving the dv/dt robustness and preventing possible false turning-on induced by system noise [ 20 , 21 , 22 ].…”

Section: Introductionmentioning

confidence: 99%

“…Considering that normally-off p-GaN gate devices feature a relatively low V T voltage, applying negative gate voltage is an important method for improving the dv/dt robustness and preventing possible false turning-on induced by system noise [ 20 , 21 , 22 ]. Nevertheless, most studies have focused on the impacts of positive gate bias stress [ 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 ], but less attention has been given to the impact of negative gate bias stress on device V T instability [ 4 , 16 , 17 , 18 ]. Elangovan et al recently analyzed the instability behavior of Schottky-type E-mode p-GaN gate power HEMTs through pulsed negative gate bias stress tests and attributed the positive threshold shift (Δ V T ) to the hole deficiency in the p-GaN region [ 17 ].…”

Section: Introductionmentioning

confidence: 99%

“…Elangovan et al recently analyzed the instability behavior of Schottky-type E-mode p-GaN gate power HEMTs through pulsed negative gate bias stress tests and attributed the positive threshold shift (Δ V T ) to the hole deficiency in the p-GaN region [ 17 ]. Zhang et al also observed positive Δ V T in the transfer characteristics of Schottky-type devices after prolonging negative gate bias stress time from 1 min to 60 min, and they attributed this positive Δ V T to hole release from donor-type traps at the p-GaN/AlGaN hetero-interface [ 18 ].…”

Section: Introductionmentioning

confidence: 99%

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Evaluation on Temperature-Dependent Transient VT Instability in p-GaN Gate HEMTs under Negative Gate Stress by Fast Sweeping Characterization

et al. 2022

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In this work, temperature-dependent transient threshold voltage (VT) instability behaviors in p-GaN/AlGaN/GaN HEMTs, with both Schottky gate (SG) and Ohmic gate (OG), were investigated systematically, under negative gate bias stress, by a fast voltage sweeping method. For SG devices, a concave-shaped VT evolution gradually occurs with the increase in temperature, and the concave peak appears faster with increasing reverse bias stress, followed by a corresponding convex-shaped VT recovery process. In contrast, the concave-shaped VT evolution for OG devices that occurred at room temperature gradually disappears in the opposite shifting direction with the increasing temperature, but the corresponding convex-shaped VT recovery process is not observed, substituted, instead, with a quick and monotonic recovery process to the initial state. To explain these interesting and different phenomena, we proposed physical mechanisms of time and temperature-dependent hole trapping, releasing, and transport, in terms of the discrepancies in barrier height and space charge region, at the metal/p-GaN junction between SG and OG HEMTs.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Evaluation on Temperature-Dependent Transient VT Instability in p-GaN Gate HEMTs under Negative Gate Stress by Fast Sweeping Characterization

et al. 2022

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“…In this p-GaN gate case, a peculiar conduction mechanism under prolonged negative gate bias stress conditions could cause device instability and degradation issues. However, few researches on device degradation and instability of p-GaN gate device under negative V GS bias stress and off-state drain stress have been reported where the hole deficiency or positive charge deficiency in the p-GaN region has considered as a mechanism behind device degradation [30,31]. In this experiment, we focused on the relations between pulsed and prolonged stress induced device degradations and instability issues.…”

Section: Prolonged Negative Gate Bias Stressmentioning

confidence: 99%

Analysis of Instability Behavior and Mechanism of E-Mode GaN Power HEMT with p-GaN Gate under Off-State Gate Bias Stress

2021

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In this study, we investigate the degradation characteristics of E-mode GaN High Electron Mobility Transistors (HEMTs) with a p-GaN gate by designed pulsed and prolonged negative gate (VGS) bias stress. Device transfer and transconductance, output, and gate-leakage characteristics were studied in detail, before and after each pulsed and prolonged negative VGS bias stress. We found that the gradual degradation of electrical parameters, such as threshold voltage (VTH) shift, on-state resistance (RDS-ON) increase, transconductance max (Gm, max) decrease, and gate leakage current (IGS-Leakage) increase, is caused by negative VGS bias stress time evolution and magnitude of stress voltage. The significance of electron trapping effects was revealed from the VTH shift or instability and other parameter degradation under different stress voltages. The degradation mechanism behind the DC characteristics could be assigned to the formation of hole deficiency at p-GaN region and trapping process at the p-GaN/AlGaN hetero-interface, which induces a change in the electric potential distribution at the gate region. The design and application of E-mode GaN with p-GaN gate power devices still need such a reliability investigation for significant credibility.

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Exploration of Physicochemical Mechanism for Negative Bias Temperature Instability in GaN‐HEMTs by Extracting Activation Energy of Dislocations

Chang

Wang

Zhou

et al. 2022

Adv Materials Inter

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epitaxial layers on silicon enables the use of existing silicon manufacturing infrastructure, eliminating the need for costly specific production facilities and leveraging large diameter silicon wafers at low cost. [10,11] Although silicon is a relatively cheap substrate compared with other substrate candidates, but has some distinct disadvantages since silicon and GaN are unmatched material systems. [12] The discrepancies in crystalline structure of GaN and silicon leads to higher lattice mismatches, behaving like dislocations and other types of defects. [13][14][15][16] The crystal defects affect the device performance and reliability to a large extent. A typical conundrum in GaN filed is related to the fact that the dislocations/lattice mismatch could exert inevitable negative effects on the device's basic performance, stability, and reliability. [17][18][19][20] Intensive researches indicated that charge trapping process caused by defects significantly affect the device performance. [21][22][23][24][25][26][27] As the most promising power device, gallium nitride (GaN)-based high electron mobility transistors (HEMTs) typically works under high voltage over a prolonged period. The long-term accumulation of heat during the operation appears to be another unfavorable factor that deteriorates the reliability. [28][29][30][31] The general degradation of electrical performance under negative bias condition at elevated temperatures is collectively known as negative bias temperature instability (NBTI) problem. [32] Although the NBTI problem was first noticed and mainly discussed in p-MOSFET devices, [33][34][35][36] it also perplexes depletion-mode or normally-ON GaN-HEMTs which is the most frequently used GaN device. [37][38][39][40][41][42][43][44] NBTI-related issues in depletion-mode GaN-HEMTs with different kinds of dielectric layer have been investigated in a series of researches. [41,[45][46][47][48][49][50] The NBTI-induced reliability issues in GaN-HEMTs have been acknowledged as a major concern that contributes to the operational instability. While intensive efforts have been made to optimize it from the perspective of manufacturing process or selected materials, [45,51,52] insufficient attention has been devoted to fundamental understanding of the intrinsic mechanisms. Some studies [41][42][43][44][45][46] attributed the degradation to the charge and discharge process of defects at the interface of GaN buffer layer and dielectric layer, while others [47][48][49][50] considered the degradation cause is not only the interface

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Electrical performances degradations and physics based mechanisms under negative bias temperature instability stress for p-GaN gate high electron mobility transistors

Cited by 12 publications

References 21 publications

Evaluation on Temperature-Dependent Transient VT Instability in p-GaN Gate HEMTs under Negative Gate Stress by Fast Sweeping Characterization

Evaluation on Temperature-Dependent Transient VT Instability in p-GaN Gate HEMTs under Negative Gate Stress by Fast Sweeping Characterization

Analysis of Instability Behavior and Mechanism of E-Mode GaN Power HEMT with p-GaN Gate under Off-State Gate Bias Stress

Exploration of Physicochemical Mechanism for Negative Bias Temperature Instability in GaN‐HEMTs by Extracting Activation Energy of Dislocations

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