In this paper, we review the nature of traps population and the transport mechanisms in GaN-on-Si E-mode MOS channel HEMTs during High Voltage Bias Temperature Instabilities (HV-BTI) test under various temperatures (T), drain voltage stress (VDSstress) and gate voltage stress (VGSstress) conditions. Thanks to experimental setup using ultra-fast ID(VG) to monitor VTH during both stress and recovery phases from 10µs to several kiloseconds. The temperature dependent measurements show that VTH and RON degradations are related to the same trap nature the CN deep acceptor traps in GaN:C layer. Two different mechanisms during the stress phase are found, first CN traps deionization, impacted by VDSstress, then the nBTI behavior influenced by VGSstress. It is found that high drain voltage stress (≥ 200V) induces a charge redistribution predominantly awards the drain node, while a lower drain voltage stress led to a charge redistribution in the source-gate region.