Analysis of Instability Behavior and Mechanism of E-Mode GaN Power HEMT with p-GaN Gate under Off-State Gate Bias Stress

Abstract

In this study, we investigate the degradation characteristics of E-mode GaN High Electron Mobility Transistors (HEMTs) with a p-GaN gate by designed pulsed and prolonged negative gate (VGS) bias stress. Device transfer and transconductance, output, and gate-leakage characteristics were studied in detail, before and after each pulsed and prolonged negative VGS bias stress. We found that the gradual degradation of electrical parameters, such as threshold voltage (VTH) shift, on-state resistance (RDS-ON) increase, transconductance max (Gm, max) decrease, and gate leakage current (IGS-Leakage) increase, is caused by negative VGS bias stress time evolution and magnitude of stress voltage. The significance of electron trapping effects was revealed from the VTH shift or instability and other parameter degradation under different stress voltages. The degradation mechanism behind the DC characteristics could be assigned to the formation of hole deficiency at p-GaN region and trapping process at the p-GaN/AlGaN hetero-interface, which induces a change in the electric potential distribution at the gate region. The design and application of E-mode GaN with p-GaN gate power devices still need such a reliability investigation for significant credibility.

Evaluation on Temperature-Dependent Transient VT Instability in p-GaN Gate HEMTs under Negative Gate Stress by Fast Sweeping Characterization

“…In contrast, the negative Δ V T results from hole accumulation. The behavior of Δ V T could be linked to three physical processes, as illustrated in Figure 8 a,b: Donor-type hole trap states at the p-GaN/AlGaN interface could be activated and release holes to the valence band in the p-GaN layer [ 17 , 18 ]; The depletion width of SCR, in the p-GaN layer of SG HEMTs, would decrease under the negative gate bias stress, which also leads to hole release [ 4 ]; Holes could flow from the gate-source drift region, towards the gate stack, and under large negative gate bias stress. Part of the holes may flow out to the gate terminal and contribute to the gate current, while part of the holes may get trapped into the gate stack region and lead to an extra hole accumulation [ 16 ].…”

“…Donor-type hole trap states at the p-GaN/AlGaN interface could be activated and release holes to the valence band in the p-GaN layer [ 17 , 18 ];…”

“…The gate bias stress-induced threshold voltage ( V T ) instability of p-GaN gate HEMTs has been widely investigated recently, and the imbalanced extra charge accumulation, caused by the (de-) trapping of holes or electrons in the gate stack region, has been proposed as the main physical cause [ 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 ]. Considering that normally-off p-GaN gate devices feature a relatively low V T voltage, applying negative gate voltage is an important method for improving the dv/dt robustness and preventing possible false turning-on induced by system noise [ 20 , 21 , 22 ].…”

“…Considering that normally-off p-GaN gate devices feature a relatively low V T voltage, applying negative gate voltage is an important method for improving the dv/dt robustness and preventing possible false turning-on induced by system noise [ 20 , 21 , 22 ]. Nevertheless, most studies have focused on the impacts of positive gate bias stress [ 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 ], but less attention has been given to the impact of negative gate bias stress on device V T instability [ 4 , 16 , 17 , 18 ]. Elangovan et al recently analyzed the instability behavior of Schottky-type E-mode p-GaN gate power HEMTs through pulsed negative gate bias stress tests and attributed the positive threshold shift (Δ V T ) to the hole deficiency in the p-GaN region [ 17 ].…”

“…Nevertheless, most studies have focused on the impacts of positive gate bias stress [ 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 ], but less attention has been given to the impact of negative gate bias stress on device V T instability [ 4 , 16 , 17 , 18 ]. Elangovan et al recently analyzed the instability behavior of Schottky-type E-mode p-GaN gate power HEMTs through pulsed negative gate bias stress tests and attributed the positive threshold shift (Δ V T ) to the hole deficiency in the p-GaN region [ 17 ]. Zhang et al also observed positive Δ V T in the transfer characteristics of Schottky-type devices after prolonging negative gate bias stress time from 1 min to 60 min, and they attributed this positive Δ V T to hole release from donor-type traps at the p-GaN/AlGaN hetero-interface [ 18 ].…”