Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs

Katti, Guruprasad; Stucchi, M.; Meyer, K. De; Dehaene, Wim

doi:10.1109/ted.2009.2034508

Cited by 518 publications

(227 citation statements)

References 9 publications

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“…The characteristics of TSVs are extracted based on [10]. An eight-plane 3-D IC (10 mm × 10 mm per plane), envisioning highly complex 3-D systems, with eight clock domains is simulated.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

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Skew variability in 3-D ICs with multiple clock domains

Pavlidis

Micheli

2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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Abstract-The effect of process variations on the clock skew in three dimensional (3-D) circuits with multiple clock domains is investigated. In 3-D ICs, the combined effect of inter-die and intra-die process variations should be considered in the design of clock distribution networks. A statistical clock skew model incorporating spatially correlated intra-die process variations is employed to describe this effect. The clock skew is shown to change in different ways with the allocation of the clock domains within the 3-D circuit. Various schemes to assign the clock domains are investigated. Different scenarios of inter-die and intra-die process variations and an intra-die spatial correlation model are applied to these schemes. An approach where each physical plane corresponds to a single clock domain is shown to be inferior to other clocking schemes for specific variation scenarios. Tradeoffs between the number of clock domains within a physical plane and the number of planes a clock tree spans are discussed and related design guidelines are offered.

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“…The characteristics of TSVs are extracted based on [10]. An eight-plane 3-D IC (10 mm × 10 mm per plane), envisioning highly complex 3-D systems, with eight clock domains is simulated.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

“…The considered 3-D technologies include these manufacturing processes where multiple physical planes bonded with different means are electrically connected by through silicon vias (TSVs) [10]. In such 3-D ICs, a clock tree can span more than one plane, where each plane is fabricated separately.…”

Section: Introductionmentioning

confidence: 99%

Skew variability in 3-D ICs with multiple clock domains

Pavlidis

Micheli

2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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“…The RLC model used in our study is shown in Fig. 1 where the resistance of this model is described as [7]: where R dc and R ac are defined as:…”

Section: Cross Talkmentioning

confidence: 99%

“…The mutual inductance of two adjacent TSVs is described by (6) where b is defined as 2d/l tsv [7]. Fig.…”

Section: Cross Talkmentioning

confidence: 99%

Parallel vs. serial inter-plane communication using TSVs

Omam

Leblebici

Micheli

2014

2014 IEEE 5th Latin American Symposium on Circuits and Systems

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“…In the previous works, several electrical models of the cylindrical TSV have been proposed [4,5,6]. Characterization of the tapered [7], annular [8,9] and coaxial [10,11,12] TSVs have been done.…”

Section: Introductionmentioning

confidence: 99%

Electrical analysis of TSV step change in radius with compensation structure

Zheng

Dong

Yang

et al. 2015

IEICE Electron. Express

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Through silicon via (TSV) is a key technology in 3-D integrated circuits (3-D ICs). At the junction of TSV and pad, an extra loss produced by the discontinuous structure is inevitable in microwave circuit, and it can not be ignored. A compensation structure which can compensate the loss from step change in radius is proposed in this paper. The conventional structure and compensation structure are simulated by High Frequency Structure Simulator (HFSS). Simulation result shows that the proposed compensation structure can effectively reduce the return loss within the whole frequency range, and the compensation of insertion loss is more obvious at higher frequency. A series of top layer compensation structures with different diameter ratios are simulated. The simulation result shows that the larger the diameter ratio, the more obvious the compensation is. As the analysis based on the impedance model of TSV correlates well with the simulations, the proposed compensation structure is a worthwhile guideline for the design of 3-D ICs.

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Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs

Cited by 518 publications

References 9 publications

Skew variability in 3-D ICs with multiple clock domains

Skew variability in 3-D ICs with multiple clock domains

Parallel vs. serial inter-plane communication using TSVs

Electrical analysis of TSV step change in radius with compensation structure

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