Coaxial through silicon via (TSV) is a promising technology in three dimensional integrated circuits (3D ICs). Conventional coaxial TSV offers shield around part of the TSV in silicon substrate leave the two ends of TSV and the whole pad without any shield. This paper reports a new coaxial TSV, which offers more shields around TSV and pad with gaps for interconnection. Furthermore, the new structure is more feasible by using double dielectrics with considering deformation and process error. The full-wave extraction simulation result shows that the new structure offers less coupling with adjacent TSVs than conventional coaxial TSV structure does. The losses of new structure is lager but can be reduced by increasing the thickness of gap.

The structural, elastic anisotropy and thermodynamic properties of the I4mm-B3C are investigated using first-principles calculations and the quasi-harmonic Debye model. The calculated elastic anisotropic suggest that I4mm-B3C is elastically anisotropic with its Poisson ratio, shear modulus, the Young modulus, the universal anisotropic index, shear anisotropic factors, and the percentage of elastic anisotropy for bulk modulus and shear modulus. The quasi-harmonic Debye model, using a set of total energy versus molar volume obtained with the firstprinciples calculations, is applied to the study of the thermal and vibrational effects. The thermal expansions, heat capacities, the Grüneisen parameters and the Debye temperatures dependence on the temperature and pressure are obtained in the whole pressure range from 0 to 90 GPa and temperature range from 0 to 2000 K.

Different from the conventional way to investigate the coupling between adjacent TSVs, we take the discharging path into consideration as the impedance of silicon substrate is actually finite. This paper first analyzes the discharging path which exists between the victim TSV and the silicon substrate, and then by transforming the tapped capacitor circuit into a RC parallel circuit for the discharging path, the frequency-dependent expressions of the parasitic elements in the discharging path are obtained. Furthermore, we vary the impedance of silicon substrate to evaluate the impact of discharging path on the coupling noise. Through simulations, it indicates that the coupling noise on the victim can be reduced significantly by lowering the impedance of discharging path.

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Through silicon via (TSV) is a key technology in 3-D integrated circuits (3-D ICs). At the junction of TSV and pad, an extra loss produced by the discontinuous structure is inevitable in microwave circuit, and it can not be ignored. A compensation structure which can compensate the loss from step change in radius is proposed in this paper. The conventional structure and compensation structure are simulated by High Frequency Structure Simulator (HFSS). Simulation result shows that the proposed compensation structure can effectively reduce the return loss within the whole frequency range, and the compensation of insertion loss is more obvious at higher frequency. A series of top layer compensation structures with different diameter ratios are simulated. The simulation result shows that the larger the diameter ratio, the more obvious the compensation is. As the analysis based on the impedance model of TSV correlates well with the simulations, the proposed compensation structure is a worthwhile guideline for the design of 3-D ICs.

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This paper proposes novel formulas for the calculation of the parasitic inductance of Tapered-Through Silicon Vias (T-TSVs), considering the TSVs located in adjacent layers. The formulas can not only be reduced to calculate the self-partial inductance and mutual-partial inductance of T-TSVs located in the same layer but also be used for cylindrical TSVs when the slope angle is 90°. The comparison between the results of the proposed formulas and Ansoft Q3D shows that the proposed formulas have very high accuracy with a maximum error of 2.5%.