Electrical impact of line-edge roughness on sub-45nm node standard cell

Abstract

As the transistors are scaled down, undesirable performance mismatch in identically designed transistors increases and hence causes greater impact on circuit performance and yield. Since Line-End Roughness (LER) has been reported to be in the order of several nanometers and not to decrease as the device shrinks, it has evolved as a critical problem in the sub-45nm devices and may lead to serious device parameter fluctuations and performance limitation for the future VLSI circuit application. Although LER is a kind of random variation, it is undesirable and has to be analyzed because it causes the device to fluctuate. In this paper, we present a new cell characterization methodology which uses the non-rectangular gate print-images generated by lithography and etch simulations with the random LER variation to estimate the device performance of a sub-45nm design. The physics based TCAD simulation tool is used for validating the accuracy of our LER model. We systematically analyze the random LER by taking the impact on circuit performance due to LER variation into consideration and suggest the maximum tolerance of LER to minimize the performance degradation. We observed that the driving current is highly affected by LER as the gate length becomes thinner. We performed lithography simulations using 45nm process window to examine the LER impact of the state-of-the-art industrial devices. Results show that the rms value of LER is as much as 10% from its nominal line edge, and the saturation current can vary by as much as 10% in our 2-input NAND cell.

Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness

“…High frequency LER induces intra-transistor variations in particular CD non-uniformity at the gate level. Low frequency LER causes inter-transistor response variations [9][10][11][12]. LER-induced variability is considered to be a serious problem in narrow transistors such as those in NAND Flash memories.…”

Analysis and optimization of process-induced electromigration on signal interconnects in 16nm FinFET SoC (system-on-chip)

“…Even though many advanced resolution enhancement techniques (RETs), such as optical proximity correction (OPC), phase-shifting mask (PSM), off-axis illumination (OAI), are applied into the metal patterning, the process variation due to the non-linear lithography process is so huge [10,18,19]. Double patterning technique (DPT) for achieving better resolution also put more variations (mask overlay issues and stitch points control) on metal patterning [11,12].…”

Patterning of Tailored Polycarbonate Based Non‐Chemically Amplified Resists Using Extreme Ultraviolet Lithography

“…LER is the deviation in pattern transfer from the photomask into the photoresist layer and can result in defects that compromise device performance. [14] A series of high-performance polycarbonates have been prepared with glass-transition temperatures and decomposition temperatures that are tunable by varying the repeat-unit chemical structure. Patterning of the polymers with extreme UV lithography has been achieved by taking advantage of direct photoinduced chain scission of the polymer chains, which results in a molecular-weight based solubility switch.…”