Electrical design of wafer level package on board for gigabit data transmission

Abstract

This paper discusses the design of a wafer level package on board for 5GHz data transmission. The design is based on the 2005 node of the International Technology Roadmap on Semiconductors (ITRS) that predicts a clock frequency of SGHz, power of 170W and an operating voltage of 0.9V for high-end microprocessors. The goal of this paper is to demonstrate the ability to support global interconnections on the board at a speed comparable to the clock frequency and supply adequate power to the chip. This requires careful design of the topology of the interconnections, control of the eddy current losses in Silicon, control of the conductor and dielectric losses in the board and design of the transition between the chip and the board. The electrical design process is discussed in detail using a test vehicle, in this paper. The test vehicle consists of Co-planar waveguide (CPW) lines on high resistivity Silicon Substrate connected to CPW lines on low k, low loss board. The transition between the chip and board is completed through solder bumps with 50um diameter and IOOum pitch. Both the Silicon and Board transmission lines have been characterized using TDR measurements. In addition, the inductance of the solder humps have been extracted. Using synthesized models extracted from measurements, the eye diagrams for 5GHz data transmission has been simulated to show the importance of losses for lmm long Silicon lines connected to 5cm long board lines through low inductance solder bumps. In addition, the effect of underfill and curing on signal propagation have been quantified.

Power distribution networks for system-on-package: status and challenges

“…15(b) along with a specified noise tolerance of 55 mV. A noise tolerance of 5% (of Vdd) indicates a WLP interconnect inductance of 50 pH, which translates to a 50-m diameter bump on 100-m pitch, details of which are available in [54].…”

Electrical/Mechanical Modeling, Reliability Assessment, and Fabrication of FlexConnects: A MEMS-Based Compliant Chip-to-Substrate Interconnect

“…Second, the inductance of the G-Helix interconnect is about 90 pH, and it is desirable to bring the inductance of a compliant off-chip interconnect as close as possible to that of an equivalent solder joint. For interconnects at a 100-μm pitch, solder bumps have an inductance of around 20-25 pH [19]. A potential solution should be cost effective and have good electrical performance without compromising mechanical performance.…”

Design and Development of Interconnects for Ultra-Fine Pitch Wafer Level Packages

“…microprocessors, high pin count logic devices, etc.). The ITRS road map [1] stated that in 2005 the high end microprocessor would have a 5 GHz clock frequency, consume 170 W of power and the operating voltage would be 0.9 V. It had been shown [2] that to support the requirements given by the ITRS road map the interconnection of the package had to fulfill some basic electrical properties such as DC resistance ≤ 25 mΩ, inductance ≤ 50 pH, and capacitance ≤ 10-15 fF. These valued were set as targets for the interconnection schemes described in this paper.…”

“…The test vehicle consisted of coplanar wave guided (CPW) lines on high resistive silicon substrate interfaced with a CPW line on a low dielectric constant and low dielectric loss board [2,4]. The transition between the chip and the board was completed through the interconnect schemes proposed earlier (BON, SSC, SBU), as shown in Fig.…”

“…13 The synthesized models extracted from the measurement results were used together with the equivalent circuit extracted for the interconnect schemes and a data transmission at 5 GHz speed had been simulated. The methodology used for model extraction was as described in [2]. The data transmission at 5 GHz was simulated using HSPICE model.…”