Abstract-In this paper, a novel method of fabricating threedimensional (3-D) system-in-package (SiP) using a silicon carrier that can integrate known good dice with an integrated cooling solution is presented. The backbone of this stacked module is the fabrication of a silicon carrier with through-hole conductive interconnects. The design, process, and assembly to fabricate silicon through-hole interconnect using a wet silicon etching method is discussed in this paper. The process optimization to fabricate silicon carriers with solder through-hole interconnect within the design tolerance has been achieved. The design and modeling methodology to optimize the package in terms of electrical aspects of the stacked module is carried out to achieve less interconnect parasitics. An integrated cooling solution for 3-D stacked modules using single-phase and two-phase cooling solutions is also demonstrated for high-power applications. Known good thin flip-chip devices with daisy chain are fabricated and attached to the silicon carrier by flip-chip processes making it a known good carrier after electrical testing. Individual known good carriers are vertically integrated to form 3-D SiP.Index Terms-Three-dimensional system-in-package (3-D SiP), stacked modules, through wafer interconnection, wafer thinning, integrated cooling solution.
Abstract-As layout density increases in highly integrated multilayer printed circuit boards (PCBs), the noise that exists in the power distribution network (PDN) is increasingly coupled to the signal traces, and precise modeling to describe the coupling phenomenon becomes necessary. This paper presents a model to describe noise coupling between the power/ground planes and signal traces in multilayer systems. An analytical model for the coupling has been successfully derived, and the coupling mechanism was rigorously analyzed and clarified. Wave equations for a signal trace with power/ground noise were solved by imposing boundary conditions. Measurements in both the frequency and time domains have been conducted to confirm the validity of the proposed model.
A vacuum package has been developed for 128x128 array 1R bolometer device with Ge window having anti reflection (AR) coating. For a good vacuum package hermeticity and low out gassing are the two critical elements. A good hermetic sealing has been achieved with Ge window attachment using solder bonding. Different metallization structures have been tried and metallization of oxide/Ti/Ni/Au with additional annealing process was found to have good adhesion and solder wetting. Getters have been activated before final vacuum sealing of the package to absorb the outgassing gases from the packaging materials. Residual Gas analysis (RGA) showed that Thermo electric cooler used inside the package outgassed more compared to other materials. Vacuum inside the package was measured by using a single element IR bolometer device and found to have vacuum of 50milli torr. The developed vacuum package has been tested hnctionally and found to be no degradation in image before and after packaging.
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