Electrical characterization of chemical and dielectric passivation of InAs nanowires

Holloway, Gregory W.; Haapamaki, Chris M.; Kuyanov, P; LaPierre, Ray; Baugh, Jonathan

doi:10.1088/0268-1242/31/11/114004

Cited by 15 publications

(15 citation statements)

References 33 publications

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“…Under a vacuum, we expect the hysteresis to be dominated by charge trapping at the SiO 2 /nanowire interface. Our results with (NH 4 ) 2 S x enable us to address the question recently raised by Holloway et al regarding whether (NH 4 ) 2 S x might be a good alternative to 1-octadecanethiol (ODT) for nanowire gate passivation. The data in Figure d–g suggests this would not be the case, which is consistent with our earlier work on GaAs also.…”

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confidence: 54%

Using Ultrathin Parylene Films as an Organic Gate Insulator in Nanowire Field-Effect Transistors

et al. 2018

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We report the development of nanowire field-effect transistors featuring an ultrathin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally coated nanowires, which we used to produce functional Ω-gate and gate-all-around structures. These give subthreshold swings as low as 140 mV/dec and on/off ratios exceeding 10 at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically treated nanowire surfaces, a feature generally not possible with oxides produced by atomic layer deposition due to the surface "self-cleaning" effect. Our results highlight the potential for parylene as an alternative ultrathin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylene's well-established biocompatible properties.

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confidence: 54%

Using Ultrathin Parylene Films as an Organic Gate Insulator in Nanowire Field-Effect Transistors

et al. 2018

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“…31,32 Slow capture and emission processes are believed to originate from trap states residing in the amorphous native oxide at the InAs NW surface and possibly even the SiO 2 gate oxide due to the large activation energies (E b ∼ 0.1−1.37 eV) and small capture cross sections (σ 0 ∼ 10 −17 −10 −19 cm 2 ) found in these experiments. Additionally, passivation of the NW surface has shown to be effective in suppressing the hysteresis in InAs NW FETs, 24,33 further supporting the claim that slow trapping processes originate from traps at the InAs NW surface and native oxide. Suppression of the G−V g hysteresis has been observed in our InAs NWs as a result of sulfur-based surface passivation and is to be reported in a later study.…”

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confidence: 73%

Surface State Dynamics Dictating Transport in InAs Nanowires

et al. 2018

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Because of their high aspect ratio, nanostructures are particularly susceptible to effects from surfaces such as slow electron trapping by surface states. However, nonequilibrium trapping dynamics have been largely overlooked when considering transport in nanoelectronic devices. In this study, we demonstrate the profound influence of dynamic trapping processes on transport in InAs nanowires through an investigation of the hysteretic and time-dependent behavior of the transconductance. We observe large densities (∼10 cm) of slow surface traps and demonstrate the ability to control and permanently fix their occupation and charge through electrostatic manipulation by the gate potential followed by thermal deactivation by cryogenic cooling. Furthermore, we observe a transition from enhancement- to depletion-mode and a 400% change in field-effect mobility within the same device when the initial gate voltage and sweep rate are varied, revealing the severe impact of electrostatic history and dynamics on InAs nanowire field-effect transistors. A time-dependent model for nanowire transconductance based on nonequilibrium carrier population dynamics with thermally activated capture and emission was constructed and showed excellent agreement with experiments, confirming the effects to be a direct result of the dynamics of slow surface traps characterized by large thermal activation barriers (∼ 700 meV). This work reveals a clear and direct link between the electrical conductivity and the microscopic interactions of charged species with nanowire surfaces and highlights the necessity for considering dynamic properties of surface states in nanoelectronic devices.

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“…While data points are too few for statistical comparison, it is a useful demonstration that nanowires can be successfully integrated with the multiplexer without any reduction in quality, since parameters compare favorably to nonmultiplexed WZ nanowires, 69 which showed V t = −7.4 V, on/off ratio = 3.4 dec, SS = 2320 mV dec −1 , n = 4.7 × 10 17 cm −3 , and μ FE = 340 cm 2 V s −1 . These measurements were performed at room temperature, which accounts for the lower mobility and higher SS 71 compared to our devices. The carrier density is larger in our measurements since an ammonium sulfide etch is performed prior to contact deposition to remove native oxide.…”

Section: Resultsmentioning

confidence: 99%

High-Throughput Electrical Characterization of Nanomaterials from Room to Cryogenic Temperatures

et al. 2020

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We present multiplexer methodology and hardware for nanoelectronic device characterization. This high-throughput and scalable approach to testing large arrays of nanodevices operates from room temperature to milli-Kelvin temperatures and is universally compatible with different materials and integration techniques. We demonstrate the applicability of our approach on two archetypal nanomaterialsgraphene and semiconductor nanowiresintegrated with a GaAs-based multiplexer using wet or dry transfer methods. A graphene film grown by chemical vapor deposition is transferred and patterned into an array of individual devices, achieving 94% yield. Device performance is evaluated using data fitting methods to obtain electrical transport metrics, showing mobilities comparable to nonmultiplexed devices fabricated on oxide substrates using wet transfer techniques. Separate arrays of indium-arsenide nanowires and micromechanically exfoliated monolayer graphene flakes are transferred using pick-and-place techniques. For the nanowire array mean values for mobility μ FE = 880/3180 cm 2 V −1 s −1 (lower/upper bound), subthreshold swing 430 mV dec −1 , and on/off ratio 3.1 decades are extracted, similar to nonmultiplexed devices. In another array, eight mechanically exfoliated graphene flakes are transferred using techniques compatible with fabrication of two-dimensional superlattices, with 75% yield. Our results are a proof-ofconcept demonstration of a versatile platform for scalable fabrication and cryogenic characterization of nanomaterial device arrays, which is compatible with a broad range of nanomaterials, transfer techniques, and device integration strategies from the forefront of quantum technology research.

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Electrical characterization of chemical and dielectric passivation of InAs nanowires

Cited by 15 publications

References 33 publications

Using Ultrathin Parylene Films as an Organic Gate Insulator in Nanowire Field-Effect Transistors

Using Ultrathin Parylene Films as an Organic Gate Insulator in Nanowire Field-Effect Transistors

Surface State Dynamics Dictating Transport in InAs Nanowires

High-Throughput Electrical Characterization of Nanomaterials from Room to Cryogenic Temperatures

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