Electrical characterization and modeling of simultaneous switching noise for leadframe packages

Miura, M.; Hirano, N.; Hiruta, Y.; Sudo, Takashi

doi:10.1109/ectc.1995.517788

Cited by 10 publications

(3 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This is due· to the electrical noise caused from impedance discontinuities, return current cross-talk, and signal cross-talk [1,2]. The electrical noise is created by the mechanical construction of the structures making up the interconnect which yields an unshielded signal path and an uncontrolled return path.…”

Section: Introductionmentioning

confidence: 99%

Fabrication process for a novel high speed coplanar-to-coaxial off-chip interconnect

McIntosh

LaMeres

2008

2008 2nd Electronics Systemintegration Technology Conference

View full text Add to dashboard Cite

Sig 0.8· V sig V bnc = N . L ret . _ = N ·L et . _ -(3) dt r t rise • ZoImpedance mismatches lead to reflections which are described by the reflection coefficient, r (equation 5). r depends on the characteristic impedance that the Finally, the inductive nature of the wire bond leads to noise in the form of reflected energy due to impedance discontinuities. The inductive properties of the wire bond lead to a relatively high impedance compared to the system (typically 50n) following equation 4. In this equation, Land C are the total inductance and capacitance of the wire bond.(4)(2)(1) JE WbThe second source of noise in a wire bonded system comes from the self inductance of the interconnect in the return path. This inductive nature of the wire bond becomes a problem when conducting return current for multiple signal nets. An L·(dijdt) noise is induced on the wire bond which manifests itself as ground and power supply bounce. Equation 3gives the amount of voltage bounce that will occur due to an inductive return path. In this equation, N signifies the number of signals that are sharing a common return path, L ret is the self inductance of the wire bond providing the return path, t rise is the 10-90 signal rise time, and Zo is the characteristic impedance of the system. electrical drawbacks [6]. The first is the unshielded nature of the wire bond leads to cross-talk between adjacent signal lines.Equations 1 and 2 give the forward and reverse cross-talk coefficients respectively for unshielded interconnect. In these expressions, C M and L M reflect the mutual capacitance and inductance between the two interconnects. C L and LL represent the self capacitance and inductance of the interconnect and vel represents the signal velocity of the signal.Anytime unshielded interconnect structures are used, there will be a non-zero mutual capacitance and mutual inductance which will lead to signal cross-talk. AbstractIn this paper, we present the design and fabrication of a novel chip-to-chip interconnect scheme for use in System-in-Package applications.The interconnect system uses an etched trench at the edge of a standard Silicon substrate to interface a miniature coaxial cable to the on-chip surface metal layers. This system delivers a shielded, matched impedance transmission path by using a coplanar structure on-chip and a coaxial structure between chips.This system is designed to be compatible with typical perimeter bonded pad sizing and spacing such that the coplanarto-coaxial transition can be selectively added to a standard wire bond process on high-speed nets.

show abstract

Section: Introductionmentioning

confidence: 99%

Fabrication process for a novel high speed coplanar-to-coaxial off-chip interconnect

McIntosh

LaMeres

2008

2008 2nd Electronics Systemintegration Technology Conference

View full text Add to dashboard Cite

show abstract

“…There has been much work into the reduction of parasitic inductance through package advancement [3,6,5]. Since the performance limitation is caused by the parasitic inductance in the level 1 and level 2 interconnects of the IC package, many packaging technologies have been developed.…”

Section: Previous Workmentioning

confidence: 99%

“…This imbalance in performance expectations between the IC and the package is a major concern for system designers. The main limitation of the package performance is the parasitic inductance present in the level 1 (from IC die to package) and level 2 (from package to board) interconnects [3,4,5]. The inductance factors that affect signal speed and integrity are as follows:…”

Section: Introductionmentioning

confidence: 99%

Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission

LaMeres

Khatri

Design, Automation and Test in Europe

View full text Add to dashboard Cite

Inductive cross-talk within IC packaging is becoming a significant bottleneck in high-speed inter-chip communication.The parasitic inductance within IC packaging causes bounce on the power supply pins in addition to glitches and rise-time degradation on the signal pins. Until recently, the parasitic inductance problem was addressed by aggressive package design. In this work we present a technique to encode the off-chip data transmission to limit bounce on the supplies and reduce inductive signal coupling due to transitions on neighboring signal lines. Both these performance limiting factors are modeled in a common mathematical framework. Our experimental results show that the proposed encoding based techniques result in reduced supply bounce and signal degradation due to inductive cross-talk, closely matching the theoretical predictions. We demonstrate that the overall bandwidth of a bus actually increases by 85% using our technique, even after accounting for the encoding overhead. The asymptotic bus size overhead is between 30% and 50%, depending on how stringent the userspecified inductive cross-talk parameters are.

show abstract

Encoding-Based Algorithm for Minimization of Inductive Cross-Talk Based on Off-Chip Data Transmission

Singha¹,

Saha²

2011

Lecture Notes in Electrical Engineering

View full text Add to dashboard Cite

Electrical characterization and modeling of simultaneous switching noise for leadframe packages

Cited by 10 publications

References 7 publications

Fabrication process for a novel high speed coplanar-to-coaxial off-chip interconnect

Fabrication process for a novel high speed coplanar-to-coaxial off-chip interconnect

Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission

Encoding-Based Algorithm for Minimization of Inductive Cross-Talk Based on Off-Chip Data Transmission

Contact Info

Product

Resources

About