Fabrication process for a novel high speed coplanar-to-coaxial off-chip interconnect

Abstract

Sig 0.8· V sig V bnc = N . L ret . _ = N ·L et . _ -(3) dt r t rise • ZoImpedance mismatches lead to reflections which are described by the reflection coefficient, r (equation 5). r depends on the characteristic impedance that the Finally, the inductive nature of the wire bond leads to noise in the form of reflected energy due to impedance discontinuities. The inductive properties of the wire bond lead to a relatively high impedance compared to the system (typically 50n) following equation 4. In this equation, Land C are the total inductance and capacitance of the wire bond.(4)(2)(1) JE WbThe second source of noise in a wire bonded system comes from the self inductance of the interconnect in the return path. This inductive nature of the wire bond becomes a problem when conducting return current for multiple signal nets. An L·(dijdt) noise is induced on the wire bond which manifests itself as ground and power supply bounce. Equation 3gives the amount of voltage bounce that will occur due to an inductive return path. In this equation, N signifies the number of signals that are sharing a common return path, L ret is the self inductance of the wire bond providing the return path, t rise is the 10-90 signal rise time, and Zo is the characteristic impedance of the system. electrical drawbacks [6]. The first is the unshielded nature of the wire bond leads to cross-talk between adjacent signal lines.Equations 1 and 2 give the forward and reverse cross-talk coefficients respectively for unshielded interconnect. In these expressions, C M and L M reflect the mutual capacitance and inductance between the two interconnects. C L and LL represent the self capacitance and inductance of the interconnect and vel represents the signal velocity of the signal.Anytime unshielded interconnect structures are used, there will be a non-zero mutual capacitance and mutual inductance which will lead to signal cross-talk. AbstractIn this paper, we present the design and fabrication of a novel chip-to-chip interconnect scheme for use in System-in-Package applications.The interconnect system uses an etched trench at the edge of a standard Silicon substrate to interface a miniature coaxial cable to the on-chip surface metal layers. This system delivers a shielded, matched impedance transmission path by using a coplanar structure on-chip and a coaxial structure between chips.This system is designed to be compatible with typical perimeter bonded pad sizing and spacing such that the coplanarto-coaxial transition can be selectively added to a standard wire bond process on high-speed nets.