Electrical characterization and mechanical modeling of process induced strain in 65 nm CMOS technology

Mobility enhancement by CESL strain in short-channel ultrathin SOI MOSFETs

“…5) measured in both structures show no major difference. It is concluded that the difference in I on is not due to V Th shift but directly reflects mobility changes [3].…”

“…Strain can be integrated in the SOI wafer (strained SOI) by using for example Smart-Cut transfer from a Si/ SiGe stack [1,2]. Strain can also be induced locally, in the transistor body, by several types of stressors: in the vertical direction by contact-etch-stop-layer CESL, in the lateral direction by sidewall stressors or in the longitudinal direction using the source/drain terminals as stressors [3]. Among these techniques, silicon nitride (CESL) is a cost-effective solution [3] that can be easily implemented in CMOS fabrication process.…”

The impacts of high tensile stress CESL and geometry design on device performance and reliability for 90nm SOI nMOSFETs

“…7(a), the I D (719 lA/lm) of device with 10 lm width and SiN380 CN layer was used as reference to estimate the deviation of I D . It is apparent that the I D increases as the gate width decreases because the compressive stress (y-axis) is increases with the gate width decreases [10][11][12][13]. Besides, previous studies [24,25] reported that nMOSFET with STI show an inverse-narrow-width effect caused by fringing electric fields, enhancing the channel edge current.…”

“…However, for deep submicron VLSI process, the compressive stress caused by shallow trench isolation (STI) would also affect devices mobility; and the STI induced compressive stress can be modified by changing the length from gate to STI edge (LOD) and gate width. Using the HS CESL to enhance device mobility has been proposed popularly and recently [2][3][4][5][6][7][8][9][10][11][12][13], but few studies studied on the interactive stress effect between the thickness of HS CESL, LOD, gate width on device characteristic and hot-carrier reliability especially for silicon-on-insulator (SOI) devices. An appropriate tensile stress will enhance device performance efficiently and avoid excess damages happen.…”

“…Therefore, a simple way that enhances devices mobility without accompanying the increase of process steps was required strongly. One of such attempts is modifying the thickness of high-tensile-stress contact etch stop layer (HS CESL) [2][3][4][5][6][7][8][9], length of diffusion (LOD) and gate width [10][11][12][13] to control the tensile and compressive stresses in channel region to improve the channel mobility.…”