Electrical and Thermal Analysis of Cu-CNT Composite TSV and GNR Interconnects

Sable, Komal; Sahoo, Manodipan

doi:10.1109/isdcs49393.2020.9262991

Cited by 5 publications

(4 citation statements)

References 19 publications

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“…After the material of the geometry is defined, the pad and TSV filling material are set to copper, the substrate material to silicon, the micro bump material to Cu 3 Sn, and the insulating layer material of the TSV to silicon dioxide, as shown in the simulation [ 30 , 31 ]. The materials used and their related physical parameters are shown in Table 1 [ 32 ].…”

Section: Methodsmentioning

confidence: 99%

Thermodynamic Multi-Field Coupling Optimization of Microsystem Based on Artificial Intelligence

Shan

et al. 2023

Micromachines

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An efficient multi-objective optimization method of temperature and stress for a microsystem based on particle swarm optimization (PSO) was established, which is used to map the relationship between through-silicon via (TSV) structural design parameters and performance objectives in the microsystem, and complete optimization temperature, stress and thermal expansion deformation efficiently. The relationship between the design and performance parameters is obtained by a finite element method (FEM) simulation model. The neural network is built and trained in order to understand the mapping relationship. Then, the design parameters are iteratively optimized using the PSO algorithm, and the FEM results are used to verify the efficiency and reliability of the optimization methods. When the optimization target of peak temperature, bump temperature, TSV temperature, maximum stress and maximum thermal deformation are set as 100 °C, 55 °C, 35 °C, 180 Mpa and 12 μm, the optimization results are as follows: the peak temperature is 97.90 °C, the bump temperature is 56.01 °C, the TSV temperature is 31.52 °C, the maximum stress is 247.4 Mpa and the maximum expansion deformation is 11.14 μm. The corresponding TSV structure design parameters are as follows: the radius of TSV is 10.28 μm, the pitch is 65 μm and the thickness of SiO2 is 0.83 μm. The error between the optimization result and the target temperature is 2.1%, 1.8%, 9.9%, 37.4% and 7.2% respectively. The PSO method has been verified by regression analysis, and the difference between the temperature and deformation optimization results of the FEM method is not more than 3%. The stress error has been analyzed, and the reliability of the developed method has been verified. While ensuring the accuracy of the results, the proposed optimization method reduces the time consumption of a single simulation from 2 h to 70 s, saves a lot of time and human resources, greatly improves the efficiency of the optimization design of microsystems, and has great significance for the development of microsystems.

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Section: Methodsmentioning

confidence: 99%

Thermodynamic Multi-Field Coupling Optimization of Microsystem Based on Artificial Intelligence

Shan

et al. 2023

Micromachines

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“…The CNTs have been used as a viable choice because of their excellent mechanical and electrical conductivity at the nanoscale [157]. Remarkably, compared to 72.9% for copper alone, the electrical resistance of a Cu-CNT composite is just 57.3%, according to Sable et al [158]. In addition, the Cu-CNT-filled TSVs with graphene nanostructures served as better interconnects than pristine Cu.…”

Section: Reliability Studies On Tsvs and Thermal Managementmentioning

confidence: 99%

Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review

Jang,

Sharma,

Jung

2023

Materials

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Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for achieving high-density integration, high-speed connectivity, and for downsizing of electronic devices. This paper describes recent developments in TSV fabrication and bonding methods in advanced 3D electronic packaging. In particular, the authors have overviewed the recent progress in the fabrication of TSV, various etching and functional layers, and conductive filling of TSVs, as well as bonding materials such as low-temperature nano-modified solders, transient liquid phase (TLP) bonding, Cu pillars, composite hybrids, and bump-free bonding, as well as the role of emerging high entropy alloy (HEA) solders in 3D microelectronic packaging. This paper serves as a guideline enumerating the current developments in 3D packaging that allow Si semiconductors to deliver improved performance and power efficiency.

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“…The temperature requirements for CNT TSVs growth have been successfully reduced to be compatible with CMOS processes. However, using CNTs as Via or in TSV still remains a challenge for mass production and industrial compatibility [ 100 , 101 ].…”

Section: Through-silicon-via (Tsv)mentioning

confidence: 99%

Recent Progress and Challenges Regarding Carbon Nanotube On-Chip Interconnects

Chen

Zhou

et al. 2022

Micromachines

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Along with deep scaling transistors and complex electronics information exchange networks, very-large-scale-integrated (VLSI) circuits require high performance and ultra-low power consumption. In order to meet the demand of data-abundant workloads and their energy efficiency, improving only the transistor performance would not be sufficient. Super high-speed microprocessors are useless if the capacity of the data lines is not increased accordingly. Meanwhile, traditional on-chip copper interconnects reach their physical limitation of resistivity and reliability and may no longer be able to keep pace with a processor’s data throughput. As one of the potential alternatives, carbon nanotubes (CNTs) have attracted important attention to become the future emerging on-chip interconnects with possible explorations of new development directions. In this paper, we focus on the electrical, thermal, and process compatibility issues of current on-chip interconnects. We review the advantages, recent developments, and dilemmas of CNT-based interconnects from the perspective of different interconnect lengths and through-silicon-via (TSV) applications.

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Electrical and Thermal Analysis of Cu-CNT Composite TSV and GNR Interconnects

Cited by 5 publications

References 19 publications

Thermodynamic Multi-Field Coupling Optimization of Microsystem Based on Artificial Intelligence

Thermodynamic Multi-Field Coupling Optimization of Microsystem Based on Artificial Intelligence

Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review

Recent Progress and Challenges Regarding Carbon Nanotube On-Chip Interconnects

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