Electrical and Data-Retention Characteristics of Two-Terminal Thyristor Random Access Memory

Highly Reliable Memory Operation of High Density Three-Terminal Thyristor Random Access Memory

“…The anode and cathode areas are highly doped with a doping concentration of 1×10 20 cm − 3 , and the doping concentration of base areas (p-and n-base) is 1×10 18 cm − 3 . The lengths of both nand p-bases are set to 100 nm considering the junctions' depletion widths [12]. The channel area is 20×20 nm 2 , and the thickness of the gate oxide is 5 nm.…”

“…The avalanche generation [24] and band-to-band tunneling [25] models are also considered to calculate the carrier generations and the tunneling. The pulses applied to all memory operations have the rise time (T rise ) and the fall time (T fall ) of 0.25 ns, while the hold time (T hold ) is 2 ns [12]. The operation speed inferred from these pulse parameters is comparable to the modern DRAM memory clock rate [26].…”

“…Even though there have been many studies to improve the capacitor technologies, such as new high-k materials [5][6][7] and a high-aspect-ratio 3D capacitor structure [8,9], these approaches possess the issue of increasing fabrication complexities and high cost [2][3]. To overcome these challenges, a capacitorless 1T DRAM structure, namely a thyristor-based random-access memory (TRAM), has been proposed as an alternative in which the charge is stored at the internal p-base and n-base storage area [10][11][12][13][14][15][16]. The TRAM can operate as a two-terminal (2-T) device by modulating the energy band with only the anode and cathode biases [10][11][12].…”

“…2-T TRAM has the advantage of its simple structure that allows a cost-effective cross-point array fabrication with conventional Si processes. Yet, the drawbacks are the low data retention and array disturbance that stem from the weak controllability of the storage area [10][11][12]. On the other hand, a three-terminal (3-T) TRAM, whose gate bias controls the energy band of the storage region, can remedy these drawbacks; the proper adjustment of gate-cathode voltage (V GC ) can improve the retention characteristics and the array disturbance immunity by anode-cathode voltage (V AC ) [13][14][15][16].…”

“…To overcome these challenges, a capacitorless 1T DRAM structure, namely a thyristor-based random-access memory (TRAM), has been proposed as an alternative in which the charge is stored at the internal p-base and n-base storage area [10][11][12][13][14][15][16]. The TRAM can operate as a two-terminal (2-T) device by modulating the energy band with only the anode and cathode biases [10][11][12]. 2-T TRAM has the advantage of its simple structure that allows a cost-effective cross-point array fabrication with conventional Si processes.…”