Electrical analyses of TSV-RDL-bump of interposers for high-speed 3D IC integration

Abstract

As the progress of the packaging technology for the electronic consuming devices, the customer demands more and more. From the trend of the development on electronic devices, it shows that these demands require for more functions or higher density of devices within a limited space. By the capabilities of the 3D-IC technology, it could support such a design with multi-purposes including a smaller size, the high-speed and multi-functions. There are many approaches and technologies to make the 3D-IC. Amount of them, the stacking with Through-Silicon-Via (TSV), plays a very important role. It shortens the path of the circuit in a device. And hence, this device may support a faster operation. In this study, we analyze the different designs based on two TSV technologies, the Cu-filled and coaxial-type TSVs. By using the simulation approach, we evaluate the performances of these proposed designs. And, the results in our study should have the benefits for designing the interposer substrates which are used for developing the 3D-IC.

Compact Models and Model Standard for 2.5D and 3D Integration

“…In general, four validation methods are applied in the previous studies: 2D/3D electromagnetic solver [9,12,4,16,19,10,13]; 3D electrostatic simulator [3,20]; vector network analyzer for frequency domain [5]; and groundsignal-ground (GSG) probing [7,11].…”

“…are necessary for full chip and full package analyses. Several work have been done to model these components [17,3,10,7,13].…”

“…The resistance path of TSV-RDL-bump and the corresponding insertion loss and return loss are evaluated [13]. The resistance discontinuity has great influence on the impedance and return loss.…”

Full channel simulation for high speed 2.5D package with silicon interposer

“…The basic structure of silicon interposer includes the RDL, the TSVs and micro-bumps [5]. The lines in the redistribution layers are covered by polymer material and the copper filled in TSVs is isolated from silicon by a thin SiO2 layer.…”

Electrical Performance Simulation of 2.5D Package

“…As the basis of 2.5D package, the wiring board on the silicon interposer density will lead to increased high-speed signal line spacing, adjacent to the crosstalk is more prone to problems. In addition, bumps and other non-continuous structure will seriously affect the high-speed signal transmission quality [6] [7] . In this paper, the signal integrity of the 2.5D package is studied in detail based on the transmission characteristics of the TSV channel and the electrical properties of the RDL high-speed signal transmission structure.…”